URL https://opencores.org/ocsvn/vspi/vspi/trunk

Subversion Repositories vspi

[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [ipcore_dir/] [coregen.cgc] - Blame information for rev 14

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   xilinx.com
   project
   coregen
   1.0
   
      
         buffermem
         
         
            buffermem
            Native
            AXI4_Full
            Memory_Slave
            false
            4
            True_Dual_Port_RAM
            No_ECC
            false
            false
            false
            Single_Bit_Error_Injection
            false
            9
            Minimum_Area
            8kx2
            true
            8
            4096
            8
            WRITE_FIRST
            Use_ENA_Pin
            32
            32
            WRITE_FIRST
            Use_ENB_Pin
            false
            false
            false
            false
            false
            false
            false
            false
            0
            false
            no_coe_file_loaded
            false
            0
            false
            false
            CE
            0
            false
            false
            CE
            0
            SYNC
            false
            100
            50
            100
            50
            100
            100
            ALL
            false
            false
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6slx45
                  spartan6
                  csg324
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  Verilog
                  false
               
               
                  2011-03-11T08:24:14.000Z
               
            
         
      
      
         spiloopmem
         
         
            spiloopmem
            Native
            AXI4_Full
            Memory_Slave
            false
            4
            Simple_Dual_Port_RAM
            No_ECC
            false
            false
            false
            Single_Bit_Error_Injection
            false
            9
            Minimum_Area
            8kx2
            false
            8
            4096
            8
            WRITE_FIRST
            Use_ENA_Pin
            8
            8
            WRITE_FIRST
            Use_ENB_Pin
            false
            false
            false
            false
            false
            false
            false
            false
            0
            false
            no_coe_file_loaded
            false
            0
            false
            false
            CE
            0
            false
            false
            CE
            0
            SYNC
            false
            100
            50
            100
            0
            100
            100
            ALL
            false
            false
            spartan6
            spartan6
            C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/
            0
            1
            0
            0
            4
            1
            9
            1
            1
            0
            no_coe_file_loaded
            0
            0
            SYNC
            0
            CE
            0
            0
            1
            0
            0
            1
            WRITE_FIRST
            8
            8
            4096
            4096
            12
            0
            CE
            0
            0
            1
            0
            0
            1
            WRITE_FIRST
            8
            8
            4096
            4096
            12
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            ALL
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6slx45
                  spartan6
                  csg324
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  Verilog
                  false
               
               
                  2011-03-11T08:24:14.000Z
               
            
            
               
                  apply_current_project_options_generator
               
               
                  customization_generator
                  
                     ./summary.log
                     unknown
                     Wed Mar 07 22:04:50 GMT 2012
                     0x5BD51164
                     generationid_615106653
                  
               
               
                  model_parameter_resolution_generator
                  
                     ./summary.log
                     unknown
                     Wed Mar 07 22:04:54 GMT 2012
                     0x5BD51164
                     generationid_615106653
                  
               
               
                  ip_xco_generator
                  
                     ./spiloopmem.xco
                     xco
                     Wed Mar 07 22:04:54 GMT 2012
                     0xEE47DCC6
                     generationid_615106653
                  
               
               
                  associated_files_generator
                  
                     ./blk_mem_gen_ds512.pdf
                     pdf
                     Tue Jun 21 05:21:31 GMT 2011
                     0xA43B8952
                     generationid_615106653
                  
                  
                     ./blk_mem_gen_v6_2_readme.txt
                     txt
                     Tue Jun 21 05:21:31 GMT 2011
                     0x399E1D72
                     generationid_615106653
                  
               
               
                  ejava_generator
                  
                     ./spiloopmem_ste/example_design/bmg_wrapper.vhd
                     ignore
                     vhdl
                     Wed Mar 07 22:04:55 GMT 2012
                     0x7F99DB77
                     generationid_615106653
                  
                  
                     ./spiloopmem_ste/example_design/spiloopmem_top.ucf
                     ignore
                     ucf
                     Wed Mar 07 22:04:55 GMT 2012
                     0x8915DFA1
                     generationid_615106653
                  
                  
                     ./spiloopmem_ste/example_design/spiloopmem_top.vhd
                     ignore
                     vhdl
                     Wed Mar 07 22:04:55 GMT 2012
                     0xAFD5224E
                     generationid_615106653
                  
                  
                     ./spiloopmem_ste/example_design/spiloopmem_top.xdc
                     ignore
                     xdc
                     Wed Mar 07 22:04:55 GMT 2012
                     0x78E2D49A
                     generationid_615106653
                  
                  
                     ./spiloopmem_ste/implement/implement.sh
                     ignore
                     unknown
                     Wed Mar 07 22:04:55 GMT 2012
                     0x452D832D
                     generationid_615106653
                  
                  
                     ./spiloopmem_ste/implement/planAhead_rdn.bat
                     ignore
                     unknown
                     Wed Mar 07 22:04:55 GMT 2012
                     0x9360D2FC
                     generationid_615106653
                  
                  
                     ./spiloopmem_ste/implement/planAhead_rdn.sh
                     ignore
                     unknown
                     Wed Mar 07 22:04:55 GMT 2012
                     0x46307551
                     generationid_615106653
                  
                  
                     ./spiloopmem_ste/implement/planAhead_rdn.tcl
                     ignore
                     tcl
                     Wed Mar 07 22:04:55 GMT 2012
                     0xEA63E4A4
                     generationid_615106653
                  
                  
                     ./spiloopmem_ste/implement/xst.prj
                     ignore
                     unknown
                     Wed Mar 07 22:04:55 GMT 2012
                     0xE2E3ED6D
                     generationid_615106653
                  
                  
                     ./spiloopmem_ste/implement/xst.scr
                     ignore
                     unknown
                     Wed Mar 07 22:04:55 GMT 2012
                     0x04885ED0
                     generationid_615106653
                  
               
               
                  ngc_netlist_generator
                  
                     ./spiloopmem.ngc
                     ngc
                     Wed Mar 07 22:05:31 GMT 2012
                     0x64C2FFF1
                     generationid_615106653
                  
               
               
                  obfuscate_netlist_generator
               
               
                  padded_implementation_netlist_generator
               
               
                  instantiation_template_generator
                  
                     ./spiloopmem.veo
                     veo
                     Wed Mar 07 22:05:33 GMT 2012
                     0xF74D6B91
                     generationid_615106653
                  
               
               
                  structural_simulation_model_generator
                  
                     ./spiloopmem.v
                     verilog
                     Wed Mar 07 22:05:33 GMT 2012
                     0xC7F34980
                     generationid_615106653
                  
               
               
                  asy_generator
                  
                     ./spiloopmem.asy
                     asy
                     Wed Mar 07 22:05:39 GMT 2012
                     0x83946D8F
                     generationid_615106653
                  
                  
                     ./summary.log
                     unknown
                     Wed Mar 07 22:05:39 GMT 2012
                     0x5BD51164
                     generationid_615106653
                  
               
               
                  xmdf_generator
                  
                     ./spiloopmem_xmdf.tcl
                     tclXmdf
                     tcl
                     Wed Mar 07 22:05:39 GMT 2012
                     0xD51D4C14
                     generationid_615106653
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Wed Mar 07 22:05:42 GMT 2012
                     0x24C9CB1C
                     generationid_615106653
                  
                  
                     ./spiloopmem.gise
                     ignore
                     gise
                     Wed Mar 07 22:05:43 GMT 2012
                     0xF8869E9A
                     generationid_615106653
                  
                  
                     ./spiloopmem.xise
                     ignore
                     xise
                     Wed Mar 07 22:05:43 GMT 2012
                     0xAB45B7A7
                     generationid_615106653
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./spiloopmem_flist.txt
                     ignore
                     txtFlist
                     txt
                     Wed Mar 07 22:05:43 GMT 2012
                     0xCE30C720
                     generationid_615106653
                  
               
               
                  view_readme_generator
               
            
         
      
   
   
      
         
            coregen
            ./
            ./tmp/
            ./tmp/_cg/
         
         
            xc6slx45
            spartan6
            csg324
            -2
         
         
            BusFormatAngleBracketNotRipped
            Verilog
            true
            Other
            false
            false
            false
            Ngc
            false
         
         
            Behavioral
            Verilog
            false
         
      
   

 

Browse

Tools

Subversion Repositories vspi

[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [ipcore_dir/] [coregen.cgc] - Blame information for rev 14

Line No.	Rev	Author	Line
1	14	mjlyons
2
3			`xilinx.com`
4			`project`
5			`coregen`
6			`1.0`
7
8
9			`buffermem`
10
11
12			`buffermem`
13			`Native`
14			`AXI4_Full`
15			`Memory_Slave`
16			`false`
17			`4`
18			`True_Dual_Port_RAM`
19			`No_ECC`
20			`false`
21			`false`
22			`false`
23			`Single_Bit_Error_Injection`
24			`false`
25			`9`
26			`Minimum_Area`
27			`8kx2`
28			`true`
29			`8`
30			`4096`
31			`8`
32			`WRITE_FIRST`
33			`Use_ENA_Pin`
34			`32`
35			`32`
36			`WRITE_FIRST`
37			`Use_ENB_Pin`
38			`false`
39			`false`
40			`false`
41			`false`
42			`false`
43			`false`
44			`false`
45			`false`
46			`0`
47			`false`
48			`no_coe_file_loaded`
49			`false`
50			`0`
51			`false`
52			`false`
53			`CE`
54			`0`
55			`false`
56			`false`
57			`CE`
58			`0`
59			`SYNC`
60			`false`
61			`100`
62			`50`
63			`100`
64			`50`
65			`100`
66			`100`
67			`ALL`
68			`false`
69			`false`
70
71
72
73
74			`coregen`
75			`./`
76			`./tmp/`
77			`./tmp/_cg/`
78
79
80			`xc6slx45`
81			`spartan6`
82			`csg324`
83			`-2`
84
85
86			`BusFormatAngleBracketNotRipped`
87			`Verilog`
88			`true`
89			`Other`
90			`false`
91			`false`
92			`false`
93			`Ngc`
94			`false`
95
96
97			`Behavioral`
98			`Verilog`
99			`false`
100
101
102			`2011-03-11T08:24:14.000Z`
103
104
105
106
107
108			`spiloopmem`
109
110
111			`spiloopmem`
112			`Native`
113			`AXI4_Full`
114			`Memory_Slave`
115			`false`
116			`4`
117			`Simple_Dual_Port_RAM`
118			`No_ECC`
119			`false`
120			`false`
121			`false`
122			`Single_Bit_Error_Injection`
123			`false`
124			`9`
125			`Minimum_Area`
126			`8kx2`
127			`false`
128			`8`
129			`4096`
130			`8`
131			`WRITE_FIRST`
132			`Use_ENA_Pin`
133			`8`
134			`8`
135			`WRITE_FIRST`
136			`Use_ENB_Pin`
137			`false`
138			`false`
139			`false`
140			`false`
141			`false`
142			`false`
143			`false`
144			`false`
145			`0`
146			`false`
147			`no_coe_file_loaded`
148			`false`
149			`0`
150			`false`
151			`false`
152			`CE`
153			`0`
154			`false`
155			`false`
156			`CE`
157			`0`
158			`SYNC`
159			`false`
160			`100`
161			`50`
162			`100`
163			`0`
164			`100`
165			`100`
166			`ALL`
167			`false`
168			`false`
169			`spartan6`
170			`spartan6`
171			`C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/`
172			`0`
173			`1`
174			`0`
175			`0`
176			`4`
177			`1`
178			`9`
179			`1`
180			`1`
181			`0`
182			`no_coe_file_loaded`
183			`0`
184			`0`
185			`SYNC`
186			`0`
187			`CE`
188			`0`
189			`0`
190			`1`
191			`0`
192			`0`
193			`1`
194			`WRITE_FIRST`
195			`8`
196			`8`
197			`4096`
198			`4096`
199			`12`
200			`0`
201			`CE`
202			`0`
203			`0`
204			`1`
205			`0`
206			`0`
207			`1`
208			`WRITE_FIRST`
209			`8`
210			`8`
211			`4096`
212			`4096`
213			`12`
214			`0`
215			`0`
216			`0`
217			`0`
218			`0`
219			`0`
220			`0`
221			`0`
222			`0`
223			`0`
224			`ALL`
225			`0`
226			`0`
227			`0`
228
229
230
231
232			`coregen`
233			`./`
234			`./tmp/`
235			`./tmp/_cg/`
236
237
238			`xc6slx45`
239			`spartan6`
240			`csg324`
241			`-2`
242
243
244			`BusFormatAngleBracketNotRipped`
245			`Verilog`
246			`true`
247			`Other`
248			`false`
249			`false`
250			`false`
251			`Ngc`
252			`false`
253
254
255			`Behavioral`
256			`Verilog`
257			`false`
258
259
260			`2011-03-11T08:24:14.000Z`
261
262
263
264
265			`apply_current_project_options_generator`
266
267
268			`customization_generator`
269
270			`./summary.log`
271			`unknown`
272			`Wed Mar 07 22:04:50 GMT 2012`
273			`0x5BD51164`
274			`generationid_615106653`
275
276
277
278			`model_parameter_resolution_generator`
279
280			`./summary.log`
281			`unknown`
282			`Wed Mar 07 22:04:54 GMT 2012`
283			`0x5BD51164`
284			`generationid_615106653`
285
286
287
288			`ip_xco_generator`
289
290			`./spiloopmem.xco`
291			`xco`
292			`Wed Mar 07 22:04:54 GMT 2012`
293			`0xEE47DCC6`
294			`generationid_615106653`
295
296
297
298			`associated_files_generator`
299
300			`./blk_mem_gen_ds512.pdf`
301			`pdf`
302			`Tue Jun 21 05:21:31 GMT 2011`
303			`0xA43B8952`
304			`generationid_615106653`
305
306
307			`./blk_mem_gen_v6_2_readme.txt`
308			`txt`
309			`Tue Jun 21 05:21:31 GMT 2011`
310			`0x399E1D72`
311			`generationid_615106653`
312
313
314
315			`ejava_generator`
316
317			`./spiloopmem_ste/example_design/bmg_wrapper.vhd`
318			`ignore`
319			`vhdl`
320			`Wed Mar 07 22:04:55 GMT 2012`
321			`0x7F99DB77`
322			`generationid_615106653`
323
324
325			`./spiloopmem_ste/example_design/spiloopmem_top.ucf`
326			`ignore`
327			`ucf`
328			`Wed Mar 07 22:04:55 GMT 2012`
329			`0x8915DFA1`
330			`generationid_615106653`
331
332
333			`./spiloopmem_ste/example_design/spiloopmem_top.vhd`
334			`ignore`
335			`vhdl`
336			`Wed Mar 07 22:04:55 GMT 2012`
337			`0xAFD5224E`
338			`generationid_615106653`
339
340
341			`./spiloopmem_ste/example_design/spiloopmem_top.xdc`
342			`ignore`
343			`xdc`
344			`Wed Mar 07 22:04:55 GMT 2012`
345			`0x78E2D49A`
346			`generationid_615106653`
347
348
349			`./spiloopmem_ste/implement/implement.sh`
350			`ignore`
351			`unknown`
352			`Wed Mar 07 22:04:55 GMT 2012`
353			`0x452D832D`
354			`generationid_615106653`
355
356
357			`./spiloopmem_ste/implement/planAhead_rdn.bat`
358			`ignore`
359			`unknown`
360			`Wed Mar 07 22:04:55 GMT 2012`
361			`0x9360D2FC`
362			`generationid_615106653`
363
364
365			`./spiloopmem_ste/implement/planAhead_rdn.sh`
366			`ignore`
367			`unknown`
368			`Wed Mar 07 22:04:55 GMT 2012`
369			`0x46307551`
370			`generationid_615106653`
371
372
373			`./spiloopmem_ste/implement/planAhead_rdn.tcl`
374			`ignore`
375			`tcl`
376			`Wed Mar 07 22:04:55 GMT 2012`
377			`0xEA63E4A4`
378			`generationid_615106653`
379
380
381			`./spiloopmem_ste/implement/xst.prj`
382			`ignore`
383			`unknown`
384			`Wed Mar 07 22:04:55 GMT 2012`
385			`0xE2E3ED6D`
386			`generationid_615106653`
387
388
389			`./spiloopmem_ste/implement/xst.scr`
390			`ignore`
391			`unknown`
392			`Wed Mar 07 22:04:55 GMT 2012`
393			`0x04885ED0`
394			`generationid_615106653`
395
396
397
398			`ngc_netlist_generator`
399
400			`./spiloopmem.ngc`
401			`ngc`
402			`Wed Mar 07 22:05:31 GMT 2012`
403			`0x64C2FFF1`
404			`generationid_615106653`
405
406
407
408			`obfuscate_netlist_generator`
409
410
411			`padded_implementation_netlist_generator`
412
413
414			`instantiation_template_generator`
415
416			`./spiloopmem.veo`
417			`veo`
418			`Wed Mar 07 22:05:33 GMT 2012`
419			`0xF74D6B91`
420			`generationid_615106653`
421
422
423
424			`structural_simulation_model_generator`
425
426			`./spiloopmem.v`
427			`verilog`
428			`Wed Mar 07 22:05:33 GMT 2012`
429			`0xC7F34980`
430			`generationid_615106653`
431
432
433
434			`asy_generator`
435
436			`./spiloopmem.asy`
437			`asy`
438			`Wed Mar 07 22:05:39 GMT 2012`
439			`0x83946D8F`
440			`generationid_615106653`
441
442
443			`./summary.log`
444			`unknown`
445			`Wed Mar 07 22:05:39 GMT 2012`
446			`0x5BD51164`
447			`generationid_615106653`
448
449
450
451			`xmdf_generator`
452
453			`./spiloopmem_xmdf.tcl`
454			`tclXmdf`
455			`tcl`
456			`Wed Mar 07 22:05:39 GMT 2012`
457			`0xD51D4C14`
458			`generationid_615106653`
459
460
461
462			`ise_generator`
463
464			`./_xmsgs/pn_parser.xmsgs`
465			`ignore`
466			`unknown`
467			`Wed Mar 07 22:05:42 GMT 2012`
468			`0x24C9CB1C`
469			`generationid_615106653`
470
471
472			`./spiloopmem.gise`
473			`ignore`
474			`gise`
475			`Wed Mar 07 22:05:43 GMT 2012`
476			`0xF8869E9A`
477			`generationid_615106653`
478
479
480			`./spiloopmem.xise`
481			`ignore`
482			`xise`
483			`Wed Mar 07 22:05:43 GMT 2012`
484			`0xAB45B7A7`
485			`generationid_615106653`
486
487
488
489			`deliver_readme_generator`
490
491
492			`flist_generator`
493
494			`./spiloopmem_flist.txt`
495			`ignore`
496			`txtFlist`
497			`txt`
498			`Wed Mar 07 22:05:43 GMT 2012`
499			`0xCE30C720`
500			`generationid_615106653`
501
502
503
504			`view_readme_generator`
505
506
507
508
509
510
511
512
513			`coregen`
514			`./`
515			`./tmp/`
516			`./tmp/_cg/`
517
518
519			`xc6slx45`
520			`spartan6`
521			`csg324`
522			`-2`
523
524
525			`BusFormatAngleBracketNotRipped`
526			`Verilog`
527			`true`
528			`Other`
529			`false`
530			`false`
531			`false`
532			`Ngc`
533			`false`
534
535
536			`Behavioral`
537			`Verilog`
538			`false`
539
540
541
542
543