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[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [ipcore_dir/] [spiloopmem.v] - Blame information for rev 14

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1 14 mjlyons
/*******************************************************************************
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*     This file is owned and controlled by Xilinx and must be used solely      *
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*     for design, simulation, implementation and creation of design files      *
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*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
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*     devices or technologies is expressly prohibited and immediately          *
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*     terminates your license.                                                 *
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*                                                                              *
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*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
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*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
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*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
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*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
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*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
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*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
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*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
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*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
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*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
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*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
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*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
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*     PARTICULAR PURPOSE.                                                      *
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*                                                                              *
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*     Xilinx products are not intended for use in life support appliances,     *
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*     devices, or systems.  Use in such applications are expressly             *
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*     prohibited.                                                              *
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*                                                                              *
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*     (c) Copyright 1995-2012 Xilinx, Inc.                                     *
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*     All rights reserved.                                                     *
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*******************************************************************************/
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// You must compile the wrapper file spiloopmem.v when simulating
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// the core, spiloopmem. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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// The synthesis directives "translate_off/translate_on" specified below are
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// supported by Xilinx, Mentor Graphics and Synplicity synthesis
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// tools. Ensure they are correct for your synthesis tool(s).
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`timescale 1ns/1ps
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module spiloopmem(
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  clka,
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  ena,
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  wea,
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  addra,
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  dina,
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  clkb,
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  enb,
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  addrb,
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  doutb
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);
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input clka;
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input ena;
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input [0 : 0] wea;
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input [11 : 0] addra;
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input [7 : 0] dina;
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input clkb;
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input enb;
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input [11 : 0] addrb;
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output [7 : 0] doutb;
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// synthesis translate_off
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  BLK_MEM_GEN_V6_2 #(
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    .C_ADDRA_WIDTH(12),
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    .C_ADDRB_WIDTH(12),
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    .C_ALGORITHM(1),
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    .C_AXI_ID_WIDTH(4),
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    .C_AXI_SLAVE_TYPE(0),
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    .C_AXI_TYPE(1),
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    .C_BYTE_SIZE(9),
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    .C_COMMON_CLK(0),
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    .C_DEFAULT_DATA("0"),
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    .C_DISABLE_WARN_BHV_COLL(0),
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    .C_DISABLE_WARN_BHV_RANGE(0),
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    .C_FAMILY("spartan6"),
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    .C_HAS_AXI_ID(0),
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    .C_HAS_ENA(1),
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    .C_HAS_ENB(1),
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    .C_HAS_INJECTERR(0),
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    .C_HAS_MEM_OUTPUT_REGS_A(0),
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    .C_HAS_MEM_OUTPUT_REGS_B(0),
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    .C_HAS_MUX_OUTPUT_REGS_A(0),
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    .C_HAS_MUX_OUTPUT_REGS_B(0),
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    .C_HAS_REGCEA(0),
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    .C_HAS_REGCEB(0),
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    .C_HAS_RSTA(0),
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    .C_HAS_RSTB(0),
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    .C_HAS_SOFTECC_INPUT_REGS_A(0),
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    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
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    .C_INIT_FILE_NAME("no_coe_file_loaded"),
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    .C_INITA_VAL("0"),
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    .C_INITB_VAL("0"),
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    .C_INTERFACE_TYPE(0),
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    .C_LOAD_INIT_FILE(0),
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    .C_MEM_TYPE(1),
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    .C_MUX_PIPELINE_STAGES(0),
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    .C_PRIM_TYPE(1),
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    .C_READ_DEPTH_A(4096),
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    .C_READ_DEPTH_B(4096),
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    .C_READ_WIDTH_A(8),
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    .C_READ_WIDTH_B(8),
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    .C_RST_PRIORITY_A("CE"),
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    .C_RST_PRIORITY_B("CE"),
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    .C_RST_TYPE("SYNC"),
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    .C_RSTRAM_A(0),
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    .C_RSTRAM_B(0),
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    .C_SIM_COLLISION_CHECK("ALL"),
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    .C_USE_BYTE_WEA(0),
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    .C_USE_BYTE_WEB(0),
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    .C_USE_DEFAULT_DATA(0),
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    .C_USE_ECC(0),
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    .C_USE_SOFTECC(0),
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    .C_WEA_WIDTH(1),
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    .C_WEB_WIDTH(1),
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    .C_WRITE_DEPTH_A(4096),
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    .C_WRITE_DEPTH_B(4096),
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    .C_WRITE_MODE_A("WRITE_FIRST"),
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    .C_WRITE_MODE_B("WRITE_FIRST"),
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    .C_WRITE_WIDTH_A(8),
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    .C_WRITE_WIDTH_B(8),
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    .C_XDEVICEFAMILY("spartan6")
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  )
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  inst (
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    .CLKA(clka),
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    .ENA(ena),
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    .WEA(wea),
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    .ADDRA(addra),
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    .DINA(dina),
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    .CLKB(clkb),
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    .ENB(enb),
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    .ADDRB(addrb),
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    .DOUTB(doutb),
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    .RSTA(),
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    .REGCEA(),
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    .DOUTA(),
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    .RSTB(),
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    .REGCEB(),
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    .WEB(),
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    .DINB(),
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    .INJECTSBITERR(),
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    .INJECTDBITERR(),
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    .SBITERR(),
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    .DBITERR(),
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    .RDADDRECC(),
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    .S_ACLK(),
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    .S_ARESETN(),
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    .S_AXI_AWID(),
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    .S_AXI_AWADDR(),
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    .S_AXI_AWLEN(),
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    .S_AXI_AWSIZE(),
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    .S_AXI_AWBURST(),
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    .S_AXI_AWVALID(),
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    .S_AXI_AWREADY(),
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    .S_AXI_WDATA(),
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    .S_AXI_WSTRB(),
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    .S_AXI_WLAST(),
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    .S_AXI_WVALID(),
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    .S_AXI_WREADY(),
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    .S_AXI_BID(),
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    .S_AXI_BRESP(),
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    .S_AXI_BVALID(),
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    .S_AXI_BREADY(),
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    .S_AXI_ARID(),
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    .S_AXI_ARADDR(),
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    .S_AXI_ARLEN(),
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    .S_AXI_ARSIZE(),
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    .S_AXI_ARBURST(),
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    .S_AXI_ARVALID(),
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    .S_AXI_ARREADY(),
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    .S_AXI_RID(),
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    .S_AXI_RDATA(),
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    .S_AXI_RRESP(),
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    .S_AXI_RLAST(),
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    .S_AXI_RVALID(),
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    .S_AXI_RREADY(),
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    .S_AXI_INJECTSBITERR(),
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    .S_AXI_INJECTDBITERR(),
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    .S_AXI_SBITERR(),
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    .S_AXI_DBITERR(),
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    .S_AXI_RDADDRECC()
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  );
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// synthesis translate_on
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endmodule

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