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1 14 mjlyons
 
2
--------------------------------------------------------------------------------
3
--
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-- BLK MEM GEN v6.2 Core - Top-level wrapper
5
--
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--------------------------------------------------------------------------------
7
--
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-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
38
-- Xilinx products are not designed or intended to be fail-
39
-- safe, or for use in any application requiring fail-safe
40
-- performance, such as life-support or safety devices or
41
-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
46
-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
48
-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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--------------------------------------------------------------------------------
55
--
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-- Filename: bmg_wrapper.vhd
57
--
58
-- Description:
59
--   This is the top-level BMG wrapper (over BMG core).
60
--
61
--------------------------------------------------------------------------------
62
-- Author: IP Solutions Division
63
--
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-- History: August 31, 2005 - First Release
65
--------------------------------------------------------------------------------
66
--
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-- Configured Core Parameter Values:
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-- (Refer to the SIM Parameters table in the datasheet for more information on
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-- the these parameters.)
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--    C_FAMILY                    :  spartan6 
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--    C_XDEVICEFAMILY             :  spartan6 
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--    C_INTERFACE_TYPE            :  0 
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--    C_AXI_TYPE                  :  1 
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--    C_AXI_SLAVE_TYPE            :  0 
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--    C_AXI_ID_WIDTH              :  4 
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--    C_MEM_TYPE                  :  1 
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--    C_BYTE_SIZE                 :  9 
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--    C_ALGORITHM                 :  1 
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--    C_PRIM_TYPE                 :  1 
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--    C_LOAD_INIT_FILE            :  0 
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--    C_INIT_FILE_NAME            :  no_coe_file_loaded 
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--    C_USE_DEFAULT_DATA          :  0 
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--    C_DEFAULT_DATA              :  0 
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--    C_RST_TYPE                  :  SYNC 
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--    C_HAS_RSTA                  :  0 
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--    C_RST_PRIORITY_A            :  CE 
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--    C_RSTRAM_A                  :  0 
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--    C_INITA_VAL                 :  0 
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--    C_HAS_ENA                   :  1 
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--    C_HAS_REGCEA                :  0 
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--    C_USE_BYTE_WEA              :  0 
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--    C_WEA_WIDTH                 :  1 
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--    C_WRITE_MODE_A              :  WRITE_FIRST 
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--    C_WRITE_WIDTH_A             :  8 
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--    C_READ_WIDTH_A              :  8 
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--    C_WRITE_DEPTH_A             :  4096 
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--    C_READ_DEPTH_A              :  4096 
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--    C_ADDRA_WIDTH               :  12 
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--    C_HAS_RSTB                  :  0 
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--    C_RST_PRIORITY_B            :  CE 
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--    C_RSTRAM_B                  :  0 
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--    C_INITB_VAL                 :  0 
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--    C_HAS_ENB                   :  1 
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--    C_HAS_REGCEB                :  0 
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--    C_USE_BYTE_WEB              :  0 
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--    C_WEB_WIDTH                 :  1 
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--    C_WRITE_MODE_B              :  WRITE_FIRST 
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--    C_WRITE_WIDTH_B             :  8 
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--    C_READ_WIDTH_B              :  8 
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--    C_WRITE_DEPTH_B             :  4096 
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--    C_READ_DEPTH_B              :  4096 
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--    C_ADDRB_WIDTH               :  12 
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--    C_HAS_MEM_OUTPUT_REGS_A     :  0 
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--    C_HAS_MEM_OUTPUT_REGS_B     :  0 
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--    C_HAS_MUX_OUTPUT_REGS_A     :  0 
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--    C_HAS_MUX_OUTPUT_REGS_B     :  0 
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--    C_HAS_SOFTECC_INPUT_REGS_A  :  0 
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--    C_HAS_SOFTECC_OUTPUT_REGS_B :  0 
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--    C_MUX_PIPELINE_STAGES       :  0 
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--    C_USE_ECC                   :  0 
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--    C_USE_SOFTECC               :  0 
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--    C_HAS_INJECTERR             :  0 
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--    C_SIM_COLLISION_CHECK       :  ALL 
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--    C_COMMON_CLK                :  0 
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--    C_DISABLE_WARN_BHV_COLL     :  0 
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--    C_DISABLE_WARN_BHV_RANGE    :  0 
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128
--------------------------------------------------------------------------------
129
-- Library Declarations
130
--------------------------------------------------------------------------------
131
 
132
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_ARITH.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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137
LIBRARY UNISIM;
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USE UNISIM.VCOMPONENTS.ALL;
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140
--------------------------------------------------------------------------------
141
-- Entity Declaration
142
--------------------------------------------------------------------------------
143
ENTITY bmg_wrapper IS
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  PORT (
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    --Port A
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    CLKA       : IN STD_LOGIC;
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    RSTA       : IN STD_LOGIC;  --opt port
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    ENA        : IN STD_LOGIC;  --optional port
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    REGCEA     : IN STD_LOGIC;  --optional port
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    WEA        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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    ADDRA      : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
152
    DINA       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
153
    DOUTA      : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
154
 
155
    --Port B
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    CLKB       : IN STD_LOGIC;
157
    RSTB       : IN STD_LOGIC;  --opt port
158
    ENB        : IN STD_LOGIC;  --optional port
159
    REGCEB     : IN STD_LOGIC;  --optional port
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    WEB        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
161
    ADDRB      : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
162
    DINB       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
163
    DOUTB      : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
164
 
165
    --ECC
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    INJECTSBITERR  : IN STD_LOGIC; --optional port
167
    INJECTDBITERR  : IN STD_LOGIC; --optional port
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    SBITERR        : OUT STD_LOGIC; --optional port
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    DBITERR        : OUT STD_LOGIC; --optional port
170
    RDADDRECC      : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port
171
 -- AXI BMG Input and Output Port Declarations
172
 
173
    -- AXI Global Signals
174
    S_ACLK                         : IN  STD_LOGIC;
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    S_AXI_AWID                     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
176
    S_AXI_AWADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
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    S_AXI_AWLEN                    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
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    S_AXI_AWSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
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    S_AXI_AWBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
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    S_AXI_AWVALID                  : IN  STD_LOGIC;
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    S_AXI_AWREADY                  : OUT STD_LOGIC;
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    S_AXI_WDATA                    : IN  STD_LOGIC_VECTOR(7  DOWNTO 0);
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    S_AXI_WSTRB                    : IN  STD_LOGIC_VECTOR(0  DOWNTO 0);
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    S_AXI_WLAST                    : IN  STD_LOGIC;
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    S_AXI_WVALID                   : IN  STD_LOGIC;
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    S_AXI_WREADY                   : OUT STD_LOGIC;
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    S_AXI_BID                      : OUT STD_LOGIC_VECTOR(3  DOWNTO 0):= (OTHERS => '0');
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    S_AXI_BRESP                    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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    S_AXI_BVALID                   : OUT STD_LOGIC;
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    S_AXI_BREADY                   : IN  STD_LOGIC;
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    -- AXI Full/Lite Slave Read (Write side)
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    S_AXI_ARID                     : IN  STD_LOGIC_VECTOR(3  DOWNTO 0);
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    S_AXI_ARADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
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    S_AXI_ARLEN                    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
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    S_AXI_ARSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
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    S_AXI_ARBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
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    S_AXI_ARVALID                  : IN  STD_LOGIC;
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    S_AXI_ARREADY                  : OUT STD_LOGIC;
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    S_AXI_RID                      : OUT STD_LOGIC_VECTOR(3  DOWNTO 0):= (OTHERS => '0');
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    S_AXI_RDATA                    : OUT STD_LOGIC_VECTOR(7  DOWNTO 0);
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    S_AXI_RRESP                    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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    S_AXI_RLAST                    : OUT STD_LOGIC;
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    S_AXI_RVALID                   : OUT STD_LOGIC;
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    S_AXI_RREADY                   : IN  STD_LOGIC;
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    -- AXI Full/Lite Sideband Signals
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    S_AXI_INJECTSBITERR            : IN  STD_LOGIC;
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    S_AXI_INJECTDBITERR            : IN  STD_LOGIC;
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    S_AXI_SBITERR                  : OUT STD_LOGIC;
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    S_AXI_DBITERR                  : OUT STD_LOGIC;
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    S_AXI_RDADDRECC                : OUT STD_LOGIC_VECTOR(11  DOWNTO 0);
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    S_ARESETN                      : IN  STD_LOGIC
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215
 
216
  );
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END bmg_wrapper;
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ARCHITECTURE xilinx OF bmg_wrapper IS
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  COMPONENT spiloopmem_top IS
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  PORT (
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      --Port A
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    ENA            : IN STD_LOGIC;  --opt port
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    WEA            : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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    ADDRA          : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
230
 
231
    DINA           : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
232
 
233
 
234
    CLKA       : IN STD_LOGIC;
235
 
236
 
237
      --Port B
238
    ENB            : IN STD_LOGIC;  --opt port
239
    ADDRB          : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
240
    DOUTB          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
241
    CLKB           : IN STD_LOGIC
242
 
243
 
244
  );
245
  END COMPONENT;
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247
BEGIN
248
 
249
  bmg0 : spiloopmem_top
250
    PORT MAP (
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      --Port A
252
      ENA        => ENA,
253
 
254
      WEA        => WEA,
255
      ADDRA      => ADDRA,
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257
      DINA       => DINA,
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259
      CLKA       => CLKA,
260
 
261
      --Port B
262
      ENB        => ENB,
263
      ADDRB      => ADDRB,
264
      DOUTB      => DOUTB,
265
      CLKB       => CLKB
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267
 
268
      );
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END xilinx;

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