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set device xc6slx45csg324-2

set projName spiloopmem

set design spiloopmem

set projDir [file dirname [info script]]

create_project $projName $projDir/results/$projName -part $device -force

set_property design_mode RTL [current_fileset -srcset]

set top_module spiloopmem_top

add_files -norecurse {../../example_design/spiloopmem_top.vhd}

add_files -norecurse {./spiloopmem.edf}

import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/spiloopmem_top.xdc}

set_property top spiloopmem_top [get_property srcset [current_run]]

synth_design

opt_design

place_design

route_design

write_sdf -rename_top_module spiloopmem_top -file routed.sdf

write_verilog -nolib -mode sim -sdf_anno false -rename_top_module spiloopmem_top routed.v

report_timing -nworst 30 -path_type full -file routed.twr

report_drc -file routed.drc

#write_bitstream