OpenCores
URL https://opencores.org/ocsvn/vspi/vspi/trunk

Subversion Repositories vspi

[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [tb1.wcfg] - Blame information for rev 14

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 14 mjlyons
2
3
   
4
   
5
   
6
      
7
         
8
            
9
            
10
         
11
      
12
   
13
   
14
   
15
      SPI_MISO
16
      SPI_MISO
17
   
18
   
19
      txMemAddr[11:0]
20
      txMemAddr[11:0]
21
      HEXRADIX
22
   
23
   
24
      txMemData[7:0]
25
      txMemData[7:0]
26
      HEXRADIX
27
   
28
   
29
      rcMemAddr[11:0]
30
      rcMemAddr[11:0]
31
      HEXRADIX
32
   
33
   
34
      rcMemData[7:0]
35
      rcMemData[7:0]
36
      HEXRADIX
37
   
38
   
39
      rcMemWE
40
      rcMemWE
41
   
42
   
43
      debug_out[7:0]
44
      debug_out[7:0]
45
   
46
   
47
      Reset
48
      Reset
49
   
50
   
51
      SysClk
52
      SysClk
53
   
54
   
55
      SPI_CLK
56
      SPI_CLK
57
   
58
   
59
      SPI_MOSI
60
      SPI_MOSI
61
   
62
   
63
      SPI_SS
64
      SPI_SS
65
   
66
   
67
      SPI_CLK_en
68
      SPI_CLK_en
69
   
70
   
71
      fdRcBytes[31:0]
72
      fdRcBytes[31:0]
73
   
74
   
75
      fdTxBytes[31:0]
76
      fdTxBytes[31:0]
77
   
78
   
79
      dummy[31:0]
80
      dummy[31:0]
81
   
82
   
83
      currRcByte[31:0]
84
      currRcByte[31:0]
85
   
86
   
87
      rcBytesNotEmpty[31:0]
88
      rcBytesNotEmpty[31:0]
89
   
90
   
91
      rcBytesStr[80:1]
92
      rcBytesStr[80:1]
93
   
94

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.