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[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [hdl/] [verilog/] [spiifc.v] - Blame information for rev 14

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Line No. Rev Author Line
1 14 mjlyons
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer: 
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// 
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// Create Date:    16:46:12 03/02/2012 
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// Design Name: 
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// Module Name:    spiifc 
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// Project Name: 
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// Target Devices: 
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// Tool versions: 
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// Description: 
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//
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// Dependencies: 
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//
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// Revision: 
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// Revision 0.01 - File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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module spiifc(
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  Reset,
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  SysClk,
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  SPI_CLK,
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  SPI_MISO,
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  SPI_MOSI,
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  SPI_SS,
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  txMemAddr,
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  txMemData,
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  rcMemAddr,
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  rcMemData,
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  rcMemWE,
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  regAddr,
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  regReadData,
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  regWriteEn,
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  regWriteData,
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  debug_out
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);
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//
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// Parameters
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//
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parameter AddrBits = 12;
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parameter RegAddrBits = 4;
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//
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// Defines
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//
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`define CMD_READ_START    8'd1
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`define CMD_READ_MORE     8'd2
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`define CMD_WRITE_START   8'd3
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`define CMD_WRITE_MORE    8'd4
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`define CMD_INTERRUPT     8'd5
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`define CMD_REG_BASE      8'd128
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`define CMD_REG_BIT       7
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`define CMD_REG_WE_BIT    6
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`define CMD_REG_ID_MASK   8'h3F
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`define STATE_GET_CMD     8'd0
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`define STATE_READING     8'd1
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`define STATE_WRITING     8'd2
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`define STATE_WRITE_INTR  8'd3
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`define STATE_BUILD_WORD  8'd4
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`define STATE_SEND_WORD   8'd5
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//
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// Input/Outputs
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//
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input                    Reset;
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input                    SysClk;
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input                    SPI_CLK;
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output                   SPI_MISO;     // outgoing (from respect of this module)
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input                    SPI_MOSI;     // incoming (from respect of this module)
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input                    SPI_SS;
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output [AddrBits-1:0]    txMemAddr;    // outgoing data
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input           [7:0]    txMemData;
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output [AddrBits-1:0]    rcMemAddr;    // incoming data
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output          [7:0]    rcMemData;
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output                   rcMemWE;
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output [RegAddrBits-1:0] regAddr;       // Register read address (combinational)
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input             [31:0] regReadData;   // Result of register read
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output                   regWriteEn;    // Enable write to register, otherwise read
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output            [31:0] regWriteData;  // Register write data
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output          [7:0] debug_out;
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//
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// Registers
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//
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reg                   SPI_CLK_reg;    // Stabalized version of SPI_CLK
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reg                   SPI_SS_reg;     // Stabalized version of SPI_SS
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reg                   SPI_MOSI_reg;   // Stabalized version of SPI_MOSI
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reg                   prev_spiClk;    // Value of SPI_CLK during last SysClk cycle
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reg                   prev_spiSS;     // Value of SPI_SS during last SysClk cycle
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reg             [7:0] state_reg;      // Register backing the 'state' wire
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reg             [7:0] rcByte_reg;     // Register backing 'rcByte'
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reg             [2:0] rcBitIndex_reg; // Register backing 'rcBitIndex'
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reg    [AddrBits-1:0] rcMemAddr_reg;  // Byte addr to write MOSI data to
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reg             [7:0] debug_reg;      // register backing debug_out signal
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reg             [2:0] txBitIndex_reg; // Register backing txBitIndex
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reg    [AddrBits-1:0] txMemAddr_reg;  // Register backing txAddr
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reg             [7:0] command;        // Command being handled
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reg            [31:0] rcWord;         // Incoming word being built
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reg             [1:0] rcWordByteId;   // Which byte the in the rcWord to map to
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reg [RegAddrBits-1:0] regAddr_reg;    // Address of register to read/write to
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//
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// Wires
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//
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wire                  risingSpiClk;       // Did the SPI_CLK rise since last SysClk cycle?
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wire                  validSpiBit;        // Are the SPI MOSI/MISO bits new and valid?
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reg             [7:0] state;              // Current state in the module's state machine (always @* effectively wire)
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wire                  rcByteValid;        // rcByte is valid and new
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wire            [7:0] rcByte;             // Byte received from master
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wire            [2:0] rcBitIndex;         // Bit of rcByte to write to next
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reg             [2:0] txBitIndex;         // bit of txByte to send to master next
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reg    [AddrBits-1:0] txMemAddr_oreg;     // Wirereg piped to txMemAddr output
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reg             [7:0] regReadByte_oreg;   // Which byte of the reg word we're reading out master
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// Save buffered SPI inputs
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always @(posedge SysClk) begin
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  SPI_CLK_reg <= SPI_CLK;
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  SPI_SS_reg <= SPI_SS;
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  SPI_MOSI_reg <= SPI_MOSI;
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end
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// Detect new valid bit
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always @(posedge SysClk) begin
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  prev_spiClk <= SPI_CLK_reg;
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end
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assign risingSpiClk = SPI_CLK_reg & (~prev_spiClk);
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assign validSpiBit = risingSpiClk & (~SPI_SS_reg);
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// Detect new SPI packet (SS dropped low)
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always @(posedge SysClk) begin
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  prev_spiSS <= SPI_SS_reg;
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end
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assign packetStart = prev_spiSS & (~SPI_SS_reg);
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// Build incoming byte
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always @(posedge SysClk) begin
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  if (validSpiBit) begin
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    rcByte_reg[rcBitIndex] <= SPI_MOSI_reg;
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    rcBitIndex_reg <= (rcBitIndex > 0 ? rcBitIndex - 1 : 7);
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  end else begin
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    rcBitIndex_reg <= rcBitIndex;
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  end
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end
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assign rcBitIndex = (Reset || packetStart ? 7 : rcBitIndex_reg);
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assign rcByte = {rcByte_reg[7:1], SPI_MOSI_reg};
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assign rcByteValid = (validSpiBit && rcBitIndex == 0 ? 1 : 0);
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// Incoming MOSI data buffer management
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assign rcMemAddr = rcMemAddr_reg;
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assign rcMemData = rcByte;
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assign rcMemWE = (state == `STATE_READING && rcByteValid ? 1 : 0);
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always @(posedge SysClk) begin
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  if (Reset || (`STATE_GET_CMD == state && rcByteValid)) begin
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    rcMemAddr_reg <= 0;
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  end else if (rcMemWE) begin
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    rcMemAddr_reg <= rcMemAddr + 1;
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  end else begin
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    rcMemAddr_reg <= rcMemAddr;
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  end
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end
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// Outgoing MISO data buffer management
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always @(*) begin
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  if (Reset || (state == `STATE_GET_CMD && rcByteValid &&
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                  (rcByte == `CMD_WRITE_START ||
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                   rcByte[`CMD_REG_BIT:`CMD_REG_WE_BIT] == 2'b11)
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                )) begin
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    txBitIndex <= 3'd7;
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    txMemAddr_oreg <= 0;
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  end else begin
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    txBitIndex <= txBitIndex_reg;
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    //txMemAddr_oreg <= txMemAddr_reg;
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    if ((state == `STATE_WRITING || state == `STATE_SEND_WORD) &&
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        validSpiBit && txBitIndex == 0) begin
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      txMemAddr_oreg <= txMemAddr_reg + 1;
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    end else begin
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      txMemAddr_oreg <= txMemAddr_reg;
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    end
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  end
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end
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always @(posedge SysClk) begin
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  if (validSpiBit && (state == `STATE_WRITING || state == `STATE_SEND_WORD)) begin
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    txBitIndex_reg <= (txBitIndex == 0 ? 7 : txBitIndex - 1);
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  end else begin
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    txBitIndex_reg <= txBitIndex;
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  end
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  txMemAddr_reg <= txMemAddr;
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//  if (state == `STATE_WRITING && validSpiBit && txBitIndex == 0) begin
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//    txMemAddr_reg <= txMemAddr + 1;
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//  end else begin
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//    txMemAddr_reg <= txMemAddr;  
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//  end
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end
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assign txMemAddr = txMemAddr_oreg;
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assign SPI_MISO = (state == `STATE_SEND_WORD ? regReadByte_oreg[txBitIndex] : txMemData[txBitIndex]);
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// State machine
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always @(*) begin
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  if (Reset || packetStart) begin
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    state <= `STATE_GET_CMD;
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// Handled in state_reg logic, should be latched, not immediate.
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//  end else if (state_reg == `STATE_GET_CMD && rcByteValid) begin
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//    state <= rcByte;
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  end else begin
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    state <= state_reg;
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  end
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end
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always @(posedge SysClk) begin
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  if (`STATE_GET_CMD == state && rcByteValid) begin
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    if (`CMD_READ_START == rcByte) begin
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      state_reg <= `STATE_READING;
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    end else if (`CMD_READ_MORE == rcByte) begin
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      state_reg <= `STATE_READING;
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    end else if (`CMD_WRITE_START == rcByte) begin
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      state_reg <= `STATE_WRITING;
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    end else if (`CMD_WRITE_MORE == rcByte) begin
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      state_reg <= `STATE_WRITING;
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    end else if (rcByte[`CMD_REG_BIT] != 0) begin
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      // Register access
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      rcWordByteId <= 0;
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      command <= `CMD_REG_BASE;               // Write reg           Read reg
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      state_reg <= (rcByte[`CMD_REG_WE_BIT] ? `STATE_BUILD_WORD : `STATE_SEND_WORD);
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    end else if (`CMD_INTERRUPT == rcByte) begin
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      // TODO: NYI
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    end
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  end else if (`STATE_BUILD_WORD == state && rcByteValid) begin
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    if (0 == rcWordByteId) begin
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      rcWord[31:24] <= rcByte;
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      rcWordByteId <= 1;
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    end else if (1 == rcWordByteId) begin
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      rcWord[23:16] <= rcByte;
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      rcWordByteId <= 2;
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    end else if (2 == rcWordByteId) begin
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      rcWord[15:8] <= rcByte;
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      rcWordByteId <= 3;
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    end else if (3 == rcWordByteId) begin
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      rcWord[7:0] <= rcByte;
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      state_reg <= `STATE_GET_CMD;
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    end
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  end else if (`STATE_SEND_WORD == state && rcByteValid) begin
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    rcWordByteId <= rcWordByteId + 1;
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    state_reg <= (rcWordByteId == 3 ? `STATE_GET_CMD : `STATE_SEND_WORD);
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  end else begin
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    state_reg <= state;
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  end
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end
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// Register logic
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assign regAddr = (`STATE_GET_CMD == state && rcByteValid && rcByte[`CMD_REG_BIT] ? (rcByte & `CMD_REG_ID_MASK) : regAddr_reg);
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assign regWriteEn = (`STATE_BUILD_WORD == state && rcByteValid && 3 == rcWordByteId ? 1 : 0);
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assign regWriteData = {rcWord[31:8], rcByte};
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always @(posedge SysClk) begin
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  regAddr_reg <= regAddr;
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end
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always @(*) begin
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  case (rcWordByteId)
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    0: regReadByte_oreg <= regReadData[31:24];
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    1: regReadByte_oreg <= regReadData[23:16];
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    2: regReadByte_oreg <= regReadData[15:8];
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    3: regReadByte_oreg <= regReadData[7:0];
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  endcase
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end
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// Debugging
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always @(posedge SysClk) begin
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  if (rcByteValid) begin
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    debug_reg <= rcByte;
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  end
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end
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assign debug_out = debug_reg;
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endmodule

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