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//----------------------------------------------------------------------------
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// user_logic.vhd - module
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//----------------------------------------------------------------------------
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//
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// ***************************************************************************
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// ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. **
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// ** **
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// ** Xilinx, Inc. **
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// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
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// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
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// ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
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// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
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// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
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// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
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// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
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// ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
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// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
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// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
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// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
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// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
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// ** FOR A PARTICULAR PURPOSE. **
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// ** **
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// ***************************************************************************
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//
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//----------------------------------------------------------------------------
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// Filename: user_logic.vhd
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// Version: 1.00.a
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// Description: User logic module.
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// Date: Wed Oct 19 16:39:24 2011 (by Create and Import Peripheral Wizard)
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// Verilog Standard: Verilog-2001
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//----------------------------------------------------------------------------
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// Naming Conventions:
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// active low signals: "*_n"
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// clock signals: "clk", "clk_div#", "clk_#x"
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// reset signals: "rst", "rst_n"
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// generics: "C_*"
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// user defined types: "*_TYPE"
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// state machine next state: "*_ns"
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// state machine current state: "*_cs"
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// combinatorial signals: "*_com"
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// pipelined or register delay signals: "*_d#"
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// counter signals: "*cnt*"
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// clock enable signals: "*_ce"
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// internal version of output port: "*_i"
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// device pins: "*_pin"
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// ports: "- Names begin with Uppercase"
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// processes: "*_PROCESS"
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// component instantiations: "<ENTITY_>I_<#|FUNC>"
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//----------------------------------------------------------------------------
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module user_logic
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(
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// -- ADD USER PORTS BELOW THIS LINE ---------------
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// --USER ports added here
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SPI_CLK,
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SPI_MISO,
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SPI_MOSI,
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SPI_SS,
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DebugLeds,
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// -- ADD USER PORTS ABOVE THIS LINE ---------------
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// -- DO NOT EDIT BELOW THIS LINE ------------------
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// -- Bus protocol ports, do not add to or delete
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Bus2IP_Clk, // Bus to IP clock
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Bus2IP_Reset, // Bus to IP reset
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Bus2IP_Addr, // Bus to IP address bus
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Bus2IP_CS, // Bus to IP chip select for user logic memory selection
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Bus2IP_RNW, // Bus to IP read/not write
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Bus2IP_Data, // Bus to IP data bus
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Bus2IP_BE, // Bus to IP byte enables
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Bus2IP_RdCE, // Bus to IP read chip enable
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Bus2IP_WrCE, // Bus to IP write chip enable
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Bus2IP_Burst, // Bus to IP burst-mode qualifier
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Bus2IP_BurstLength, // Bus to IP burst length
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Bus2IP_RdReq, // Bus to IP read request
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Bus2IP_WrReq, // Bus to IP write request
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IP2Bus_AddrAck, // IP to Bus address acknowledgement
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IP2Bus_Data, // IP to Bus data bus
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IP2Bus_RdAck, // IP to Bus read transfer acknowledgement
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IP2Bus_WrAck, // IP to Bus write transfer acknowledgement
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IP2Bus_Error, // IP to Bus error response
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IP2Bus_IntrEvent // IP to Bus interrupt event
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// -- DO NOT EDIT ABOVE THIS LINE ------------------
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); // user_logic
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// -- ADD USER PARAMETERS BELOW THIS LINE ------------
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// --USER parameters added here
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// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
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// -- DO NOT EDIT BELOW THIS LINE --------------------
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// -- Bus protocol parameters, do not add to or delete
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parameter C_SLV_AWIDTH = 32;
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parameter C_SLV_DWIDTH = 32;
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parameter C_NUM_REG = 16;
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parameter C_NUM_MEM = 1;
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parameter C_NUM_INTR = 1;
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// -- DO NOT EDIT ABOVE THIS LINE --------------------
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// -- ADD USER PORTS BELOW THIS LINE -----------------
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// --USER ports added here
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input SPI_CLK;
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output SPI_MISO;
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input SPI_MOSI;
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input SPI_SS;
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output [0:7] DebugLeds;
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// -- ADD USER PORTS ABOVE THIS LINE -----------------
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// -- DO NOT EDIT BELOW THIS LINE --------------------
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// -- Bus protocol ports, do not add to or delete
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input Bus2IP_Clk;
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input Bus2IP_Reset;
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input [0 : C_SLV_AWIDTH-1] Bus2IP_Addr;
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input [0 : C_NUM_MEM-1] Bus2IP_CS;
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input Bus2IP_RNW;
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input [0 : C_SLV_DWIDTH-1] Bus2IP_Data;
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input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE;
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input [0 : C_NUM_REG-1] Bus2IP_RdCE;
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input [0 : C_NUM_REG-1] Bus2IP_WrCE;
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input Bus2IP_Burst;
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input [0 : 8] Bus2IP_BurstLength;
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input Bus2IP_RdReq;
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input Bus2IP_WrReq;
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output IP2Bus_AddrAck;
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output [0 : C_SLV_DWIDTH-1] IP2Bus_Data;
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output IP2Bus_RdAck;
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output IP2Bus_WrAck;
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output IP2Bus_Error;
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output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
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// -- DO NOT EDIT ABOVE THIS LINE --------------------
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//----------------------------------------------------------------------------
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// Implementation
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//----------------------------------------------------------------------------
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// --USER nets declarations added here, as needed for user logic
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assign DebugLeds = debugLedsReg;
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reg [7:0] debugLedsReg;
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// Nets for user logic slave model s/w accessible register example
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reg [0 : C_SLV_DWIDTH-1] slv_reg0;
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reg [0 : C_SLV_DWIDTH-1] slv_reg1;
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reg [0 : C_SLV_DWIDTH-1] slv_reg2;
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reg [0 : C_SLV_DWIDTH-1] slv_reg3;
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reg [0 : C_SLV_DWIDTH-1] slv_reg4;
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reg [0 : C_SLV_DWIDTH-1] slv_reg5;
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reg [0 : C_SLV_DWIDTH-1] slv_reg6;
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reg [0 : C_SLV_DWIDTH-1] slv_reg7;
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reg [0 : C_SLV_DWIDTH-1] slv_reg8;
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reg [0 : C_SLV_DWIDTH-1] slv_reg9;
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reg [0 : C_SLV_DWIDTH-1] slv_reg10;
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reg [0 : C_SLV_DWIDTH-1] slv_reg11;
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reg [0 : C_SLV_DWIDTH-1] slv_reg12;
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reg [0 : C_SLV_DWIDTH-1] slv_reg13;
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reg [0 : C_SLV_DWIDTH-1] slv_reg14;
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reg [0 : C_SLV_DWIDTH-1] slv_reg15;
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wire [0 : 15] slv_reg_write_sel;
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wire [0 : 15] slv_reg_read_sel;
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reg [0 : C_SLV_DWIDTH-1] slv_ip2bus_data;
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wire slv_read_ack;
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wire slv_write_ack;
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integer byte_index, bit_index;
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// --USER logic implementation added here
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wire [11:0] SpiIfcMemAddr;
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wire [7:0] SpiIfcMemData;
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spiifc spiIfc(
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.Reset(Bus2IP_Reset),
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.SPI_CLK(SPI_CLK),
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.SPI_MISO(SPI_MISO),
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.SPI_MOSI(SPI_MOSI),
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.SPI_SS(SPI_SS),
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.txMemAddr(SpiIfcMemAddr),
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.txMemData(SpiIfcMemData)
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);
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wire [31:0] douta_dummy;
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wire [ 7:0] dinb_dummy;
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assign dinb_dummy = 8'h00;
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wire [11:0] byteAddr;
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spimem your_instance_name (
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.clka(Bus2IP_Clk), // input clka
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.ena(Bus2IP_CS[0] & (~Bus2IP_RNW) & Bus2IP_WrReq), // input ena
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.wea(1'b1), // input [0 : 0] wea
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.addra({Bus2IP_Addr[20:29]}), // input [9 : 0] addra
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.dina({Bus2IP_Data}), // input [31 : 0] dina
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.douta(douta_dummy), // output [31 : 0] douta
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.clkb(SPI_CLK), // input clkb
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.enb(1'b1), // input enb
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.web(1'b0), // input [0 : 0] web
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.addrb(SpiIfcMemAddr), // input [11 : 0] addrb
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.dinb(dinb_dummy), // input [7 : 0] dinb
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.doutb(SpiIfcMemData) // output [7 : 0] doutb
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);
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// ------------------------------------------------------
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// Example code to read/write user logic slave model s/w accessible registers
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//
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// Note:
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// The example code presented here is to show you one way of reading/writing
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// software accessible registers implemented in the user logic slave model.
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// Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
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// to one software accessible register by the top level template. For example,
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// if you have four 32 bit software accessible registers in the user logic,
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// you are basically operating on the following memory mapped registers:
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//
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// Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
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// "1000" C_BASEADDR + 0x0
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// "0100" C_BASEADDR + 0x4
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// "0010" C_BASEADDR + 0x8
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// "0001" C_BASEADDR + 0xC
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//
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// ------------------------------------------------------
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assign
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slv_reg_write_sel = Bus2IP_WrCE[0:15],
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slv_reg_read_sel = Bus2IP_RdCE[0:15],
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slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15],
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slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15];
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// implement slave model register(s)
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always @( posedge Bus2IP_Clk )
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begin: SLAVE_REG_WRITE_PROC
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debugLedsReg <= {Bus2IP_CS[0], Bus2IP_RNW, Bus2IP_WrReq, IP2Bus_WrAck, 3'b0011};
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if ( Bus2IP_Reset == 1 )
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begin
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slv_reg0 <= 0;
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slv_reg1 <= 0;
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slv_reg2 <= 0;
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slv_reg3 <= 0;
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slv_reg4 <= 0;
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slv_reg5 <= 0;
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slv_reg6 <= 0;
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slv_reg7 <= 0;
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slv_reg8 <= 0;
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slv_reg9 <= 0;
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slv_reg10 <= 0;
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slv_reg11 <= 0;
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slv_reg12 <= 0;
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slv_reg13 <= 0;
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slv_reg14 <= 0;
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slv_reg15 <= 0;
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end
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else
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case ( slv_reg_write_sel )
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16'b1000000000000000 :
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for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
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if ( Bus2IP_BE[byte_index] == 1 )
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for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
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slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
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16'b0100000000000000 :
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for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
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if ( Bus2IP_BE[byte_index] == 1 )
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for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
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slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
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16'b0010000000000000 :
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for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
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if ( Bus2IP_BE[byte_index] == 1 )
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for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
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slv_reg2[bit_index] <= Bus2IP_Data[bit_index];
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16'b0001000000000000 :
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for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
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if ( Bus2IP_BE[byte_index] == 1 )
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for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
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slv_reg3[bit_index] <= Bus2IP_Data[bit_index];
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16'b0000100000000000 :
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for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
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if ( Bus2IP_BE[byte_index] == 1 )
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for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
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slv_reg4[bit_index] <= Bus2IP_Data[bit_index];
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16'b0000010000000000 :
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for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
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if ( Bus2IP_BE[byte_index] == 1 )
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for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
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slv_reg5[bit_index] <= Bus2IP_Data[bit_index];
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16'b0000001000000000 :
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for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
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| 279 |
|
|
if ( Bus2IP_BE[byte_index] == 1 )
|
| 280 |
|
|
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
|
| 281 |
|
|
slv_reg6[bit_index] <= Bus2IP_Data[bit_index];
|
| 282 |
|
|
16'b0000000100000000 :
|
| 283 |
|
|
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
|
| 284 |
|
|
if ( Bus2IP_BE[byte_index] == 1 )
|
| 285 |
|
|
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
|
| 286 |
|
|
slv_reg7[bit_index] <= Bus2IP_Data[bit_index];
|
| 287 |
|
|
16'b0000000010000000 :
|
| 288 |
|
|
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
|
| 289 |
|
|
if ( Bus2IP_BE[byte_index] == 1 )
|
| 290 |
|
|
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
|
| 291 |
|
|
slv_reg8[bit_index] <= Bus2IP_Data[bit_index];
|
| 292 |
|
|
16'b0000000001000000 :
|
| 293 |
|
|
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
|
| 294 |
|
|
if ( Bus2IP_BE[byte_index] == 1 )
|
| 295 |
|
|
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
|
| 296 |
|
|
slv_reg9[bit_index] <= Bus2IP_Data[bit_index];
|
| 297 |
|
|
16'b0000000000100000 :
|
| 298 |
|
|
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
|
| 299 |
|
|
if ( Bus2IP_BE[byte_index] == 1 )
|
| 300 |
|
|
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
|
| 301 |
|
|
slv_reg10[bit_index] <= Bus2IP_Data[bit_index];
|
| 302 |
|
|
16'b0000000000010000 :
|
| 303 |
|
|
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
|
| 304 |
|
|
if ( Bus2IP_BE[byte_index] == 1 )
|
| 305 |
|
|
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
|
| 306 |
|
|
slv_reg11[bit_index] <= Bus2IP_Data[bit_index];
|
| 307 |
|
|
16'b0000000000001000 :
|
| 308 |
|
|
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
|
| 309 |
|
|
if ( Bus2IP_BE[byte_index] == 1 )
|
| 310 |
|
|
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
|
| 311 |
|
|
slv_reg12[bit_index] <= Bus2IP_Data[bit_index];
|
| 312 |
|
|
16'b0000000000000100 :
|
| 313 |
|
|
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
|
| 314 |
|
|
if ( Bus2IP_BE[byte_index] == 1 )
|
| 315 |
|
|
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
|
| 316 |
|
|
slv_reg13[bit_index] <= Bus2IP_Data[bit_index];
|
| 317 |
|
|
16'b0000000000000010 :
|
| 318 |
|
|
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
|
| 319 |
|
|
if ( Bus2IP_BE[byte_index] == 1 )
|
| 320 |
|
|
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
|
| 321 |
|
|
slv_reg14[bit_index] <= Bus2IP_Data[bit_index];
|
| 322 |
|
|
16'b0000000000000001 :
|
| 323 |
|
|
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
|
| 324 |
|
|
if ( Bus2IP_BE[byte_index] == 1 )
|
| 325 |
|
|
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
|
| 326 |
|
|
slv_reg15[bit_index] <= Bus2IP_Data[bit_index];
|
| 327 |
|
|
default : ;
|
| 328 |
|
|
endcase
|
| 329 |
|
|
|
| 330 |
|
|
end // SLAVE_REG_WRITE_PROC
|
| 331 |
|
|
|
| 332 |
|
|
// implement slave model register read mux
|
| 333 |
|
|
always @( slv_reg_read_sel or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 or slv_reg8 or slv_reg9 or slv_reg10 or slv_reg11 or slv_reg12 or slv_reg13 or slv_reg14 or slv_reg15 )
|
| 334 |
|
|
begin: SLAVE_REG_READ_PROC
|
| 335 |
|
|
|
| 336 |
|
|
case ( slv_reg_read_sel )
|
| 337 |
|
|
16'b1000000000000000 : slv_ip2bus_data <= slv_reg0;
|
| 338 |
|
|
16'b0100000000000000 : slv_ip2bus_data <= slv_reg1;
|
| 339 |
|
|
16'b0010000000000000 : slv_ip2bus_data <= slv_reg2;
|
| 340 |
|
|
16'b0001000000000000 : slv_ip2bus_data <= slv_reg3;
|
| 341 |
|
|
16'b0000100000000000 : slv_ip2bus_data <= slv_reg4;
|
| 342 |
|
|
16'b0000010000000000 : slv_ip2bus_data <= slv_reg5;
|
| 343 |
|
|
16'b0000001000000000 : slv_ip2bus_data <= slv_reg6;
|
| 344 |
|
|
16'b0000000100000000 : slv_ip2bus_data <= slv_reg7;
|
| 345 |
|
|
16'b0000000010000000 : slv_ip2bus_data <= slv_reg8;
|
| 346 |
|
|
16'b0000000001000000 : slv_ip2bus_data <= slv_reg9;
|
| 347 |
|
|
16'b0000000000100000 : slv_ip2bus_data <= slv_reg10;
|
| 348 |
|
|
16'b0000000000010000 : slv_ip2bus_data <= slv_reg11;
|
| 349 |
|
|
16'b0000000000001000 : slv_ip2bus_data <= slv_reg12;
|
| 350 |
|
|
16'b0000000000000100 : slv_ip2bus_data <= slv_reg13;
|
| 351 |
|
|
16'b0000000000000010 : slv_ip2bus_data <= slv_reg14;
|
| 352 |
|
|
16'b0000000000000001 : slv_ip2bus_data <= slv_reg15;
|
| 353 |
|
|
default : slv_ip2bus_data <= 0;
|
| 354 |
|
|
endcase
|
| 355 |
|
|
|
| 356 |
|
|
end // SLAVE_REG_READ_PROC
|
| 357 |
|
|
|
| 358 |
|
|
// ------------------------------------------------------------
|
| 359 |
|
|
// Example code to drive IP to Bus signals
|
| 360 |
|
|
// ------------------------------------------------------------
|
| 361 |
|
|
|
| 362 |
|
|
assign IP2Bus_AddrAck = slv_write_ack || slv_read_ack;
|
| 363 |
|
|
assign IP2Bus_Data = slv_ip2bus_data;
|
| 364 |
|
|
assign IP2Bus_WrAck = slv_write_ack;
|
| 365 |
|
|
assign IP2Bus_RdAck = slv_read_ack;
|
| 366 |
|
|
assign IP2Bus_Error = 0;
|
| 367 |
|
|
|
| 368 |
|
|
endmodule
|
