Subversion Repositories vtach

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'DATA' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG1' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG2' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG3' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG4' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG5' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG6' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG7' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG8' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG9' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG10' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG11' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG12' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG13' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG14' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected input port 'TRIG15' of component 'chipscope_ila' is tied to default value.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/ila_pro_0.vhd" line 43: Unconnected output port 'TRIG_OUT' of component 'chipscope_ila'.

"/home/alw/projects/vtachspartan/_ngo/cs_ila_pro_0/tmp/_cg/_bbx/chipscope_ila_v1_04_a/ila_core.vhd" line 874: Unconnected output port 'WR_TSTAMP_OVERFLOW' of component 'ila_cap_storage'.

Input <CONTROL_I<3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CONTROL_I<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <tmpCompData0<2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <tmpCompData<2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <sel<11:10>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <sel<7:6>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <sel<3:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <din_dly2<11>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <din_dly1<11>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <comp<11:3>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <cfg_data<11:3>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iO> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <logic_0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <logic_0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <iOUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <logic_0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <iOUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <tmpCompData0<2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <tmpCompData<2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <sel<15:10>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <sel<9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <sel<7:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <din_dly1<15>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <comp<15:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <cfg_data<15:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <DOPB> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <logic_1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <sel> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <logic_1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <logic_0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <din_dly2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <din_dly1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <comp> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <cfg_data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <state_set> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <final_out> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <buffered_match<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <sel> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <logic_1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <logic_0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <din_dly1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <comp> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <cfg_data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <lowAddr_tc_1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <lowAddr_tc_0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <lowAddr_tc> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <lowAddr_rst> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <lowAddr_inv> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <lowAddr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <highAddr_d> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <localDOB> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <localDOA_padded> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <localADDRB<14:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <localADDRA<14>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Input <CAP_ENDSTATE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <ENDSTATE_dstat> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <DSTAT_reset> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <DSTAT7> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <DSTAT6> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <DSTAT3> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <DSTAT2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Input <WR_TSTAMP> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <WR_GAP> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RD_TSTAMP_EN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <WR_REWIND> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <WR_RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <logic_1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <logic_0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <logic_0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <logic_1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <iMATCH_TC<7:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iCFG_EN_VEC> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iCFG_DOUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iCFG_DATA> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Input <TRIGGER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <REWIND> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <logic_0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <iSCNT_load> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <cfg_data_vec<32:17>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Input <CFG_EN_16_0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_EN_16_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <tstamp_d> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <logic_1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <iTSTAMP_OUTQ> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iTSTAMP_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iREWIND_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iGAP_OUTQQ> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iGAP_OUTQ> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iGAP_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <gapout_d> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <cfg_data<11>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <CFG_CTRL_EN_VEC<15:8>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <logic_1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <iTRIGGER> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iMATCH_TC> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iENDSTATE> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iCFG_SEQ_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iCFG_EN_VEC> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.

Signal <iCFG_DOUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iCFG_DATA<17:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iCAPTURE_n> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Input <TRIG_RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_EN_16_0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_EN_16_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <logic_1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <countCfgIn> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <cfg_data<1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <CFG_MC_EN_VEC> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <CFG_MC_EN> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <logic_1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <countCfgIn> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <cfg_data<1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <CFG_TRIGMCNT_EN_VEC> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <CFG_TRIGMCNT_EN> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Input <CONTROL_IN<34:20>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CONTROL_IN<17:14>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CONTROL_IN<10:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CONTROL_IN<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <ATC_CLKIN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <iTRIG_SRL> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iTRIG_OUT_SET> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iTRIG_OUT_1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iTRIG_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iHALT> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <iCFG_TSEQ_DOUT> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <iCFG_EN_VEC> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.

Signal <iCFG_EN_16_1> is used but never assigned. This sourceless signal will be automatically connected to value 0.

Signal <iCFG_EN_16_0> is used but never assigned. This sourceless signal will be automatically connected to value 0.

Signal <iCAP_EXT_TRIGOUT> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Output <TRIG_OUT> is never assigned. Tied to value 0.

Input <TRIG10<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG11<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG12<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG13<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG14<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG15<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG1<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG2<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG3<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG4<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG5<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG6<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG7<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG8<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG9<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <DATA<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <logic_1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <iTRIG_OUT> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Signal <iDATA> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Signal <iCONTROL_IN<17:15>> is used but never assigned. This sourceless signal will be automatically connected to value 000.

Signal <iATC_CLKIN> is used but never assigned. This sourceless signal will be automatically connected to value 0.

Signal <ATC_CLKIN> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Instance I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i in unit I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i of type RAMB16_S1_S36 has been replaced by RAMB16

HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.