OpenCores
URL https://opencores.org/ocsvn/vtach/vtach/trunk

Subversion Repositories vtach

[/] [vtach/] [trunk/] [_xmsgs/] [pn_parser.xmsgs] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 wd5gnr
2
3
4
5
6
7
8
9 
 
10
11 
Analyzing Verilog file \"/home/alw/projects/vtachspartan/alu.v\" into library work
12
13 
 
14 
Analyzing Verilog file \"/home/alw/projects/vtachspartan/bcdadd.v\" into library work
15
16 
 
17 
Analyzing Verilog file \"/home/alw/projects/vtachspartan/bcdincr.v\" into library work
18
19 
 
20 
Analyzing Verilog file \"/home/alw/projects/vtachspartan/bcdneg.v\" into library work
21
22 
 
23 
Analyzing Verilog file \"/home/alw/projects/vtachspartan/debounce.v\" into library work
24
25 
 
26 
Analyzing Verilog file \"/home/alw/projects/vtachspartan/digitadd.v\" into library work
27
28 
 
29 
Analyzing Verilog file \"/home/alw/projects/vtachspartan/display.v\" into library work
30
31 
 
32 
Analyzing Verilog file \"/home/alw/projects/vtachspartan/io_input.v\" into library work
33
34 
 
35 
Analyzing Verilog file \"/home/alw/projects/vtachspartan/io_output.v\" into library work
36
37 
 
38 
Analyzing Verilog file \"/home/alw/projects/vtachspartan/memory.v\" into library work
39
40 
 
41 
Analyzing Verilog file \"/home/alw/projects/vtachspartan/usum.v\" into library work
42
43 
 
44 
Analyzing Verilog file \"/home/alw/projects/vtachspartan/vtach.v\" into library work
45
46 
 
47
48 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.