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[/] [vtach/] [trunk/] [fuse.log] - Blame information for rev 2
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wd5gnr |
Running: /opt/Xilinx/13.2/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "/home/alw/projects/vtachspartan/bcdadd_tb_isim_beh.exe" -prj "/home/alw/projects/vtachspartan/bcdadd_tb_beh.prj" "work.bcdadd_tb" "work.glbl"
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ISim O.61xd (signature 0xb4d1ced7)
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Number of CPUs detected in this system: 6
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Turning on mult-threading, number of parallel sub-compilation jobs: 12
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Determining compilation order of HDL files
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Analyzing Verilog file \"/home/alw/projects/vtachspartan/digitadd.v\" into library work
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Analyzing Verilog file \"/home/alw/projects/vtachspartan/bcdincr.v\" into library work
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Analyzing Verilog file \"/home/alw/projects/vtachspartan/bcdadd.v\" into library work
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Analyzing Verilog file \"/home/alw/projects/vtachspartan/bcdadd_tb.v\" into library work
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Analyzing Verilog file \"/opt/Xilinx/13.2/ISE_DS/ISE//verilog/src/glbl.v\" into library work
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Starting static elaboration
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WARNING:HDLCompiler:189 - "/home/alw/projects/vtachspartan/bcdadd.v" Line 5: Size mismatch in connection of port . Formal port size is 17-bit while actual signal size is 16-bit.
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WARNING:HDLCompiler:189 - "/home/alw/projects/vtachspartan/bcdadd.v" Line 12: Size mismatch in connection of port . Formal port size is 17-bit while actual signal size is 12-bit.
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Completed static elaboration
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Fuse Memory Usage: 79368 KB
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Fuse CPU Usage: 70 ms
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Compiling module digitadd
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Compiling module bcdincr
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Compiling module bcdneg17
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Compiling module bcdneg13
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Compiling module usum
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Compiling module bcdadd
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Compiling module bcdadd_tb
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Compiling module glbl
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Time Resolution for simulation is 1ps.
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Waiting for 1 sub-compilation(s) to finish...
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Compiled 8 Verilog Units
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Built simulation executable /home/alw/projects/vtachspartan/bcdadd_tb_isim_beh.exe
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Fuse Memory Usage: 901744 KB
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Fuse CPU Usage: 100 ms
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GCC CPU Usage: 170 ms
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