URL https://opencores.org/ocsvn/vtach/vtach/trunk

Subversion Repositories vtach

[/] [vtach/] [trunk/] [ipcore_dir/] [coregen.cgp] - Blame information for rev 2

Details | Compare with Previous | View Log


SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc3s1000
SET devicefamily = spartan3
SET flowvendor = Other
SET package = ft256
SET speedgrade = -4
SET verilogsim = true
SET vhdlsim = false

Line No.	Rev	Author	Line
1	2	wd5gnr	`SET busformat = BusFormatAngleBracketNotRipped`
2			`SET designentry = Verilog`
3			`SET device = xc3s1000`
4			`SET devicefamily = spartan3`
5			`SET flowvendor = Other`
6			`SET package = ft256`
7			`SET speedgrade = -4`
8			`SET verilogsim = true`
9			`SET vhdlsim = false`

Browse

Tools

Subversion Repositories vtach

[/] [vtach/] [trunk/] [ipcore_dir/] [coregen.cgp] - Blame information for rev 2