URL
https://opencores.org/ocsvn/vtach/vtach/trunk
[/] [vtach/] [trunk/] [ipcore_dir/] [summary.log] - Blame information for rev 2
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
2 |
wd5gnr |
|
| 2 |
|
|
User Configuration
|
| 3 |
|
|
-------------------------------------
|
| 4 |
|
|
Algorithm : Minimum_Area
|
| 5 |
|
|
Memory Type : Single_Port_RAM
|
| 6 |
|
|
Port A Read Width : 13
|
| 7 |
|
|
Port A Write Width : 13
|
| 8 |
|
|
Memory Depth : 100
|
| 9 |
|
|
--------------------------------------------------------------
|
| 10 |
|
|
|
| 11 |
|
|
Block RAM resource(s) (18K BRAMs) : 1
|
| 12 |
|
|
--------------------------------------------------------------
|
| 13 |
|
|
Clock A Frequency : 100
|
| 14 |
|
|
Port A Enable Rate : 100
|
| 15 |
|
|
Port A Write Rate : 50
|
| 16 |
|
|
----------------------------------------------------------
|
| 17 |
|
|
Estimated Power for IP : 7.121394 mW
|
| 18 |
|
|
----------------------------------------------------------
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
