URL https://opencores.org/ocsvn/vtach/vtach/trunk

Subversion Repositories vtach

[/] [vtach/] [trunk/] [iseconfig/] [vtachspartan.projectmgr] - Blame information for rev 2

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         2
         /top |home|alw|projects|vtachspartan|vtach.v/bugadder - bcdincr
         /top |home|alw|projects|vtachspartan|vtach.v/execunit - alu/adder - bcdadd/adder - usum
         /top |home|alw|projects|vtachspartan|vtach.v/execunit - alu/adder - bcdadd/bneg - bcdneg13
         /top |home|alw|projects|vtachspartan|vtach.v/execunit - alu/adder - bcdadd/zneg - bcdneg17
      
      
         clockdll - mainclock (/home/alw/projects/vtachspartan/ipcore_dir/mainclock.xaw)
      
      8
      0
      000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000194000000020000000000000000000000000200000064ffffffff000000810000000300000002000001940000000100000003000000000000000100000003
      true
      clockdll - mainclock (/home/alw/projects/vtachspartan/ipcore_dir/mainclock.xaw)
   
   
      
         1
         Configure Target Device
         Design Utilities
         Implement Design
         Synthesize - XST
         User Constraints
      
      
         
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000164000000010000000100000000000000000000000064ffffffff000000810000000000000001000001640000000100000000
      false
      
   
   
      
         1
      
      
      0
      0
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000b1c000000040101000100000000000000000000000064ffffffff0000008100000000000000040000007e00000001000000000000010c00000001000000000000008f0000000100000000000009030000000100000000
      false
      alu.v
   
   
      
         1
         work
      
      
      0
      0
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000164000000010001000100000000000000000000000064ffffffff000000810000000000000001000001640000000100000000
      false
      work
   
   000000ff0000000000000002000001870000012001000000060100000002
   Implementation
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f1000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f10000000100000000
      false
      
   
   
      
         1
         User Constraints
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f9000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f90000000100000000
      false
      
   
   
      
         2
         /bcdadd_tb |home|alw|projects|vtachspartan|bcdadd_tb.v
         /vtach_test |home|alw|projects|vtachspartan|vtach_test.v
      
      
         vtach_test (/home/alw/projects/vtachspartan/vtach_test.v)
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010a000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010a0000000100000003000000000000000100000003
      false
      vtach_test (/home/alw/projects/vtachspartan/vtach_test.v)
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f9000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f90000000100000000
      false
      
   
   
      
         1
         ISim Simulator
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f9000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f90000000100000000
      false
      
   
   
      
         1
      
      
         
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000164000000010000000100000000000000000000000064ffffffff000000810000000000000001000001640000000100000000
      false
      
   
   
      
         1
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f1000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f10000000100000000
      false
      
   
   
      
         1
      
      
         CORE Generator
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f1000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f10000000100000000
      false
      CORE Generator
   


Line No.	Rev	Author	Line
1	2	wd5gnr
2
3
4
5
6
7
8
9			`2`
10			`/top \|home\|alw\|projects\|vtachspartan\|vtach.v/bugadder - bcdincr`
11			`/top \|home\|alw\|projects\|vtachspartan\|vtach.v/execunit - alu/adder - bcdadd/adder - usum`
12			`/top \|home\|alw\|projects\|vtachspartan\|vtach.v/execunit - alu/adder - bcdadd/bneg - bcdneg13`
13			`/top \|home\|alw\|projects\|vtachspartan\|vtach.v/execunit - alu/adder - bcdadd/zneg - bcdneg17`
14
15
16			`clockdll - mainclock (/home/alw/projects/vtachspartan/ipcore_dir/mainclock.xaw)`
17
18			`8`
19			`0`
20			`000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000194000000020000000000000000000000000200000064ffffffff000000810000000300000002000001940000000100000003000000000000000100000003`
21			`true`
22			`clockdll - mainclock (/home/alw/projects/vtachspartan/ipcore_dir/mainclock.xaw)`
23
24
25
26			`1`
27			`Configure Target Device`
28			`Design Utilities`
29			`Implement Design`
30			`Synthesize - XST`
31			`User Constraints`
32
33
34
35
36			`0`
37			`0`
38			`000000ff00000000000000010000000100000000000000000000000000000000000000000000000164000000010000000100000000000000000000000064ffffffff000000810000000000000001000001640000000100000000`
39			`false`
40
41
42
43
44			`1`
45
46
47			`0`
48			`0`
49			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000b1c000000040101000100000000000000000000000064ffffffff0000008100000000000000040000007e00000001000000000000010c00000001000000000000008f0000000100000000000009030000000100000000`
50			`false`
51			`alu.v`
52
53
54
55			`1`
56			`work`
57
58
59			`0`
60			`0`
61			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000164000000010001000100000000000000000000000064ffffffff000000810000000000000001000001640000000100000000`
62			`false`
63			`work`
64
65			`000000ff0000000000000002000001870000012001000000060100000002`
66			`Implementation`
67
68
69			`1`
70			`Design Utilities`
71
72
73
74
75			`0`
76			`0`
77			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f1000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f10000000100000000`
78			`false`
79
80
81
82
83			`1`
84			`User Constraints`
85
86
87
88
89			`0`
90			`0`
91			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f9000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f90000000100000000`
92			`false`
93
94
95
96
97			`2`
98			`/bcdadd_tb \|home\|alw\|projects\|vtachspartan\|bcdadd_tb.v`
99			`/vtach_test \|home\|alw\|projects\|vtachspartan\|vtach_test.v`
100
101
102			`vtach_test (/home/alw/projects/vtachspartan/vtach_test.v)`
103
104			`0`
105			`0`
106			`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010a000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010a0000000100000003000000000000000100000003`
107			`false`
108			`vtach_test (/home/alw/projects/vtachspartan/vtach_test.v)`
109
110
111
112			`1`
113			`Design Utilities`
114
115
116
117
118			`0`
119			`0`
120			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f9000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f90000000100000000`
121			`false`
122
123
124
125
126			`1`
127			`ISim Simulator`
128
129
130
131
132			`0`
133			`0`
134			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f9000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f90000000100000000`
135			`false`
136
137
138
139
140			`1`
141
142
143
144
145			`0`
146			`0`
147			`000000ff00000000000000010000000100000000000000000000000000000000000000000000000164000000010000000100000000000000000000000064ffffffff000000810000000000000001000001640000000100000000`
148			`false`
149
150
151
152
153			`1`
154
155
156
157
158			`0`
159			`0`
160			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f1000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f10000000100000000`
161			`false`
162
163
164
165
166			`1`
167
168
169			`CORE Generator`
170
171			`0`
172			`0`
173			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f1000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f10000000100000000`
174			`false`
175			`CORE Generator`
176
177

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Subversion Repositories vtach

[/] [vtach/] [trunk/] [iseconfig/] [vtachspartan.projectmgr] - Blame information for rev 2