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https://opencores.org/ocsvn/vtach/vtach/trunk
[/] [vtach/] [trunk/] [mainclock_arwz.ucf] - Blame information for rev 2
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wd5gnr |
# Generated by Xilinx Architecture Wizard
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# --- UCF Template Only ---
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# Cut and paste these attributes into the project's UCF file, if desired
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INST DCM_INST CLK_FEEDBACK = 1X;
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INST DCM_INST CLKDV_DIVIDE = 2.0;
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INST DCM_INST CLKFX_DIVIDE = 25;
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INST DCM_INST CLKFX_MULTIPLY = 16;
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INST DCM_INST CLKIN_DIVIDE_BY_2 = FALSE;
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INST DCM_INST CLKIN_PERIOD = 20.000;
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INST DCM_INST CLKOUT_PHASE_SHIFT = NONE;
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INST DCM_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
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INST DCM_INST DFS_FREQUENCY_MODE = LOW;
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INST DCM_INST DLL_FREQUENCY_MODE = LOW;
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INST DCM_INST DUTY_CYCLE_CORRECTION = TRUE;
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INST DCM_INST FACTORY_JF = 8080;
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INST DCM_INST PHASE_SHIFT = 0;
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INST DCM_INST STARTUP_WAIT = FALSE;
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