Subversion Repositories vtach

# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator

create_project -name vtachspartan -dir "/home/alw/projects/vtachspartan/planAhead_run_1" -part xc3s1000ft256-4

set_param project.pinAheadLayout yes

set srcset [get_property srcset [current_run -impl]]

set_property top top $srcset

set_param project.paUcfFile  "vtach.ucf"

add_files [list {ipcore_dir/mainmem.ngc}]

set hdlfile [add_files [list {digitadd.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

set hdlfile [add_files [list {bcdincr.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

set hdlfile [add_files [list {usum.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

set hdlfile [add_files [list {display.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

set hdlfile [add_files [list {bcdneg.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

set hdlfile [add_files [list {ipcore_dir/mainmem.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

set hdlfile [add_files [list {io_output.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

set hdlfile [add_files [list {io_input.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

set hdlfile [add_files [list {debounce.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

set hdlfile [add_files [list {bcdadd.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

set hdlfile [add_files [list {memory.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

set hdlfile [add_files [list {mainclock.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

set hdlfile [add_files [list {alu.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

set hdlfile [add_files [list {vtach.v}]]

set_property file_type Verilog $hdlfile

set_property library work $hdlfile

add_files "vtach.ucf" -fileset [get_property constrset [current_run]]

add_files "ipcore_dir/mainmem.ncf" -fileset [get_property constrset [current_run]]

open_rtl_design -part xc3s1000ft256-4