| 1 |
2 |
wd5gnr |
//! **************************************************************************
|
| 2 |
|
|
// Written by: Map O.61xd on Sat May 25 07:43:36 2013
|
| 3 |
|
|
//! **************************************************************************
|
| 4 |
|
|
|
| 5 |
|
|
SCHEMATIC START;
|
| 6 |
|
|
PROHIBIT = SITE "C3";
|
| 7 |
|
|
PROHIBIT = SITE "D2";
|
| 8 |
|
|
PROHIBIT = SITE "D1";
|
| 9 |
|
|
PROHIBIT = SITE "E2";
|
| 10 |
|
|
PROHIBIT = SITE "E1";
|
| 11 |
|
|
PROHIBIT = SITE "F5";
|
| 12 |
|
|
PROHIBIT = SITE "G2";
|
| 13 |
|
|
PROHIBIT = SITE "G1";
|
| 14 |
|
|
PROHIBIT = SITE "J1";
|
| 15 |
|
|
PROHIBIT = SITE "K1";
|
| 16 |
|
|
PROHIBIT = SITE "K2";
|
| 17 |
|
|
PROHIBIT = SITE "M1";
|
| 18 |
|
|
PROHIBIT = SITE "M2";
|
| 19 |
|
|
PROHIBIT = SITE "N1";
|
| 20 |
|
|
PROHIBIT = SITE "N2";
|
| 21 |
|
|
PROHIBIT = SITE "P2";
|
| 22 |
|
|
PROHIBIT = SITE "M16";
|
| 23 |
|
|
PROHIBIT = SITE "M15";
|
| 24 |
|
|
PROHIBIT = SITE "T14";
|
| 25 |
|
|
PROHIBIT = SITE "P5";
|
| 26 |
|
|
PROHIBIT = SITE "N5";
|
| 27 |
|
|
PROHIBIT = SITE "R9";
|
| 28 |
|
|
PROHIBIT = SITE "T10";
|
| 29 |
|
|
PROHIBIT = SITE "N10";
|
| 30 |
|
|
PROHIBIT = SITE "R11";
|
| 31 |
|
|
PROHIBIT = SITE "T12";
|
| 32 |
|
|
PROHIBIT = SITE "R12";
|
| 33 |
|
|
PROHIBIT = SITE "R4";
|
| 34 |
|
|
COMP "ds0" LOCATE = SITE "D14" LEVEL 1;
|
| 35 |
|
|
COMP "ds1" LOCATE = SITE "G14" LEVEL 1;
|
| 36 |
|
|
COMP "ds2" LOCATE = SITE "F14" LEVEL 1;
|
| 37 |
|
|
COMP "ds3" LOCATE = SITE "E13" LEVEL 1;
|
| 38 |
|
|
COMP "pb0" LOCATE = SITE "M13" LEVEL 1;
|
| 39 |
|
|
COMP "pb1" LOCATE = SITE "M14" LEVEL 1;
|
| 40 |
|
|
COMP "pb2" LOCATE = SITE "L13" LEVEL 1;
|
| 41 |
|
|
COMP "clk" LOCATE = SITE "T9" LEVEL 1;
|
| 42 |
|
|
COMP "segA" LOCATE = SITE "E14" LEVEL 1;
|
| 43 |
|
|
COMP "segB" LOCATE = SITE "G13" LEVEL 1;
|
| 44 |
|
|
COMP "segC" LOCATE = SITE "N15" LEVEL 1;
|
| 45 |
|
|
COMP "segD" LOCATE = SITE "P15" LEVEL 1;
|
| 46 |
|
|
COMP "segE" LOCATE = SITE "R16" LEVEL 1;
|
| 47 |
|
|
COMP "segF" LOCATE = SITE "F13" LEVEL 1;
|
| 48 |
|
|
COMP "segG" LOCATE = SITE "N16" LEVEL 1;
|
| 49 |
|
|
COMP "sw<0>" LOCATE = SITE "F12" LEVEL 1;
|
| 50 |
|
|
COMP "sw<1>" LOCATE = SITE "G12" LEVEL 1;
|
| 51 |
|
|
COMP "sw<2>" LOCATE = SITE "H14" LEVEL 1;
|
| 52 |
|
|
COMP "sw<3>" LOCATE = SITE "H13" LEVEL 1;
|
| 53 |
|
|
COMP "sw<4>" LOCATE = SITE "J14" LEVEL 1;
|
| 54 |
|
|
COMP "sw<5>" LOCATE = SITE "J13" LEVEL 1;
|
| 55 |
|
|
COMP "sw<6>" LOCATE = SITE "K14" LEVEL 1;
|
| 56 |
|
|
COMP "sw<7>" LOCATE = SITE "K13" LEVEL 1;
|
| 57 |
|
|
COMP "led<0>" LOCATE = SITE "K12" LEVEL 1;
|
| 58 |
|
|
COMP "led<1>" LOCATE = SITE "P14" LEVEL 1;
|
| 59 |
|
|
COMP "led<2>" LOCATE = SITE "L12" LEVEL 1;
|
| 60 |
|
|
COMP "led<3>" LOCATE = SITE "N14" LEVEL 1;
|
| 61 |
|
|
COMP "led<4>" LOCATE = SITE "P13" LEVEL 1;
|
| 62 |
|
|
COMP "led<5>" LOCATE = SITE "N12" LEVEL 1;
|
| 63 |
|
|
COMP "led<6>" LOCATE = SITE "P12" LEVEL 1;
|
| 64 |
|
|
COMP "led<7>" LOCATE = SITE "P11" LEVEL 1;
|
| 65 |
|
|
COMP "extreset" LOCATE = SITE "L14" LEVEL 1;
|
| 66 |
|
|
PIN
|
| 67 |
|
|
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A_pins<10>
|
| 68 |
|
|
= BEL
|
| 69 |
|
|
"mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A"
|
| 70 |
|
|
PINNAME CLKA;
|
| 71 |
|
|
PIN
|
| 72 |
|
|
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B_pins<10>
|
| 73 |
|
|
= BEL
|
| 74 |
|
|
"mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B"
|
| 75 |
|
|
PINNAME CLKB;
|
| 76 |
|
|
TIMEGRP clockdll_CLKFX_BUF = BEL "clkdiv" PIN
|
| 77 |
|
|
"mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A_pins<10>"
|
| 78 |
|
|
PIN
|
| 79 |
|
|
"mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B_pins<10>"
|
| 80 |
|
|
BEL "clockdll/CLKFX_BUFG_INST.GCLKMUX" BEL "clockdll/CLKFX_BUFG_INST";
|
| 81 |
|
|
PIN clockdll/DCM_INST_pins<3> = BEL "clockdll/DCM_INST" PINNAME CLKIN;
|
| 82 |
|
|
TIMEGRP clk = PIN "clockdll/DCM_INST_pins<3>";
|
| 83 |
|
|
TS_clk = PERIOD TIMEGRP "clk" 50 MHz HIGH 50%;
|
| 84 |
|
|
TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP "clockdll_CLKFX_BUF" TS_clk * 0.64 HIGH
|
| 85 |
|
|
50%;
|
| 86 |
|
|
SCHEMATIC END;
|
| 87 |
|
|
|
