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Release 13.2 Map O.61xd (lin64)
Xilinx Mapping Report File for Design 'top'
 
Design Information
------------------
Command Line   : map -filter iseconfig/filter.filter -intstyle ise -p
xc3s1000-ft256-4 -timing -logic_opt on -ol high -xe n -t 1 -register_duplication
on -cm speed -ir off -ignore_keep_hierarchy -pr off -power off -o top_map.ncd
top.ngd top.pcf
Target Device  : xc3s1000
Target Package : ft256
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date    : Sat May 25 07:43:29 2013
 
Design Summary
--------------
Number of errors:      0
Number of warnings:   51
Logic Utilization:
  Number of Slice Flip Flops:           237 out of  15,360    1%
  Number of 4 input LUTs:               557 out of  15,360    3%
Logic Distribution:
  Number of occupied Slices:            347 out of   7,680    4%
    Number of Slices containing only related logic:     347 out of     347 100%
    Number of Slices containing unrelated logic:          0 out of     347   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:         597 out of  15,360    3%
    Number used as logic:               557
    Number used as a route-thru:         40
 
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
 
  Number of bonded IOBs:                 32 out of     173   18%
  Number of RAMB16s:                      1 out of      24    4%
  Number of BUFGMUXs:                     3 out of       8   37%
  Number of DCMs:                         1 out of       4   25%
 
Average Fanout of Non-Clock Nets:                3.29
 
Peak Memory Usage:  429 MB
Total REAL time to MAP completion:  7 secs
Total CPU time to MAP completion:   7 secs
 
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
 
Section 1 - Errors
------------------
 
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
WARNING:PhysDesignRules:812 - Dangling pin  on
   block:
   str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.
 
Section 3 - Informational
-------------------------
INFO:Security:54 - 'xc3s1000' is a WebPack part.
INFO:MapLib:562 - No environment variables are currently set.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
   1.260 Volts)
INFO:Pack:1650 - Map created a placed design.
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp clockdll/DCM_INST,
   consult the device Interactive Data Sheet.
 
Section 4 - Removed Logic Summary
---------------------------------
   4 block(s) optimized away
 
Section 5 - Removed Logic
-------------------------
 
Optimized Block(s):
TYPE            BLOCK
GND             XST_GND
VCC             XST_VCC
GND             mem/ram/XST_GND
VCC             mem/ram/XST_VCC
 
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
 
Section 6 - IOB Properties
--------------------------
 
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| clk                                | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| ds0                                | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| ds1                                | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| ds2                                | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| ds3                                | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| extreset                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| led<0>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| led<1>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| led<2>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| led<3>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| led<4>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| led<5>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| led<6>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| led<7>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| pb0                                | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| pb1                                | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| pb2                                | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| segA                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| segB                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| segC                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| segD                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| segE                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| segF                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| segG                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | FAST |              |          |          |
| sw<0>                              | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw<1>                              | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw<2>                              | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw<3>                              | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw<4>                              | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw<5>                              | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw<6>                              | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw<7>                              | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
 
Section 7 - RPMs
----------------
 
Section 8 - Guide Report
------------------------
Guide not run on this design.
 
Section 9 - Area Group and Partition Summary
--------------------------------------------
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
Area Group Information
----------------------
 
  No area groups were found in this design.
 
----------------------
 
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
 
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
 
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
 
Section 12 - Control Set Information
------------------------------------
No control set information for this architecture.
 
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.

Line No.	Rev	Author	Line
1	2	wd5gnr	`Release 13.2 Map O.61xd (lin64)`
2			`Xilinx Mapping Report File for Design 'top'`
3
4			`Design Information`
5			`------------------`
6			`Command Line : map -filter iseconfig/filter.filter -intstyle ise -p`
7			`xc3s1000-ft256-4 -timing -logic_opt on -ol high -xe n -t 1 -register_duplication`
8			`on -cm speed -ir off -ignore_keep_hierarchy -pr off -power off -o top_map.ncd`
9			`top.ngd top.pcf`
10			`Target Device : xc3s1000`
11			`Target Package : ft256`
12			`Target Speed : -4`
13			`Mapper Version : spartan3 -- $Revision: 1.55 $`
14			`Mapped Date : Sat May 25 07:43:29 2013`
15
16			`Design Summary`
17			`--------------`
18			`Number of errors: 0`
19			`Number of warnings: 51`
20			`Logic Utilization:`
21			`Number of Slice Flip Flops: 237 out of 15,360 1%`
22			`Number of 4 input LUTs: 557 out of 15,360 3%`
23			`Logic Distribution:`
24			`Number of occupied Slices: 347 out of 7,680 4%`
25			`Number of Slices containing only related logic: 347 out of 347 100%`
26			`Number of Slices containing unrelated logic: 0 out of 347 0%`
27			`*See NOTES below for an explanation of the effects of unrelated logic.`
28			`Total Number of 4 input LUTs: 597 out of 15,360 3%`
29			`Number used as logic: 557`
30			`Number used as a route-thru: 40`
31
32			`The Slice Logic Distribution report is not meaningful if the design is`
33			`over-mapped for a non-slice resource or if Placement fails.`
34
35			`Number of bonded IOBs: 32 out of 173 18%`
36			`Number of RAMB16s: 1 out of 24 4%`
37			`Number of BUFGMUXs: 3 out of 8 37%`
38			`Number of DCMs: 1 out of 4 25%`
39
40			`Average Fanout of Non-Clock Nets: 3.29`
41
42			`Peak Memory Usage: 429 MB`
43			`Total REAL time to MAP completion: 7 secs`
44			`Total CPU time to MAP completion: 7 secs`
45
46			`Table of Contents`
47			`-----------------`
48			`Section 1 - Errors`
49			`Section 2 - Warnings`
50			`Section 3 - Informational`
51			`Section 4 - Removed Logic Summary`
52			`Section 5 - Removed Logic`
53			`Section 6 - IOB Properties`
54			`Section 7 - RPMs`
55			`Section 8 - Guide Report`
56			`Section 9 - Area Group and Partition Summary`
57			`Section 10 - Timing Report`
58			`Section 11 - Configuration String Information`
59			`Section 12 - Control Set Information`
60			`Section 13 - Utilization by Hierarchy`
61
62			`Section 1 - Errors`
63			`------------------`
64
65			`Section 2 - Warnings`
66			`--------------------`
67			`WARNING:Security:42 - Your software subscription period has lapsed. Your current`
68			`version of Xilinx tools will continue to function, but you no longer qualify for`
69			`Xilinx software updates or new releases.`
70			`WARNING:PhysDesignRules:812 - Dangling pin on`
71			`block:`
72			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
73			`WARNING:PhysDesignRules:812 - Dangling pin on`
74			`block:`
75			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
76			`WARNING:PhysDesignRules:812 - Dangling pin on`
77			`block:`
78			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
79			`WARNING:PhysDesignRules:812 - Dangling pin on`
80			`block:`
81			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
82			`WARNING:PhysDesignRules:812 - Dangling pin on`
83			`block:`
84			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
85			`WARNING:PhysDesignRules:812 - Dangling pin on`
86			`block:`
87			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
88			`WARNING:PhysDesignRules:812 - Dangling pin on`
89			`block:`
90			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
91			`WARNING:PhysDesignRules:812 - Dangling pin on`
92			`block:`
93			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
94			`WARNING:PhysDesignRules:812 - Dangling pin on`
95			`block:`
96			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
97			`WARNING:PhysDesignRules:812 - Dangling pin on`
98			`block:`
99			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
100			`WARNING:PhysDesignRules:812 - Dangling pin on`
101			`block:`
102			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
103			`WARNING:PhysDesignRules:812 - Dangling pin on`
104			`block:`
105			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
106			`WARNING:PhysDesignRules:812 - Dangling pin on`
107			`block:`
108			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
109			`WARNING:PhysDesignRules:812 - Dangling pin on`
110			`block:`
111			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
112			`WARNING:PhysDesignRules:812 - Dangling pin on`
113			`block:`
114			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
115			`WARNING:PhysDesignRules:812 - Dangling pin on`
116			`block:`
117			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
118			`WARNING:PhysDesignRules:812 - Dangling pin on`
119			`block:`
120			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
121			`WARNING:PhysDesignRules:812 - Dangling pin on`
122			`block:`
123			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
124			`WARNING:PhysDesignRules:812 - Dangling pin on`
125			`block:`
126			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
127			`WARNING:PhysDesignRules:812 - Dangling pin on`
128			`block:`
129			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
130			`WARNING:PhysDesignRules:812 - Dangling pin on`
131			`block:`
132			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
133			`WARNING:PhysDesignRules:812 - Dangling pin on`
134			`block:`
135			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
136			`WARNING:PhysDesignRules:812 - Dangling pin on`
137			`block:`
138			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
139			`WARNING:PhysDesignRules:812 - Dangling pin on`
140			`block:`
141			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
142			`WARNING:PhysDesignRules:812 - Dangling pin on`
143			`block:`
144			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:.`
145			`WARNING:PhysDesignRules:812 - Dangling pin on`
146			`block:`
147			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
148			`WARNING:PhysDesignRules:812 - Dangling pin on`
149			`block:`
150			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
151			`WARNING:PhysDesignRules:812 - Dangling pin on`
152			`block:`
153			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
154			`WARNING:PhysDesignRules:812 - Dangling pin on`
155			`block:`
156			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
157			`WARNING:PhysDesignRules:812 - Dangling pin on`
158			`block:`
159			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
160			`WARNING:PhysDesignRules:812 - Dangling pin on`
161			`block:`
162			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
163			`WARNING:PhysDesignRules:812 - Dangling pin on`
164			`block:`
165			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
166			`WARNING:PhysDesignRules:812 - Dangling pin on`
167			`block:`
168			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
169			`WARNING:PhysDesignRules:812 - Dangling pin on`
170			`block:`
171			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
172			`WARNING:PhysDesignRules:812 - Dangling pin on`
173			`block:`
174			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
175			`WARNING:PhysDesignRules:812 - Dangling pin on`
176			`block:`
177			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
178			`WARNING:PhysDesignRules:812 - Dangling pin on`
179			`block:`
180			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
181			`WARNING:PhysDesignRules:812 - Dangling pin on`
182			`block:`
183			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
184			`WARNING:PhysDesignRules:812 - Dangling pin on`
185			`block:`
186			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
187			`WARNING:PhysDesignRules:812 - Dangling pin on`
188			`block:`
189			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
190			`WARNING:PhysDesignRules:812 - Dangling pin on`
191			`block:`
192			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
193			`WARNING:PhysDesignRules:812 - Dangling pin on`
194			`block:`
195			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
196			`WARNING:PhysDesignRules:812 - Dangling pin on`
197			`block:`
198			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
199			`WARNING:PhysDesignRules:812 - Dangling pin on`
200			`block:`
201			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
202			`WARNING:PhysDesignRules:812 - Dangling pin on`
203			`block:`
204			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
205			`WARNING:PhysDesignRules:812 - Dangling pin on`
206			`block:`
207			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
208			`WARNING:PhysDesignRules:812 - Dangling pin on`
209			`block:`
210			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
211			`WARNING:PhysDesignRules:812 - Dangling pin on`
212			`block:`
213			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
214			`WARNING:PhysDesignRules:812 - Dangling pin on`
215			`block:`
216			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
217			`WARNING:PhysDesignRules:812 - Dangling pin on`
218			`block:`
219			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
220			`WARNING:PhysDesignRules:812 - Dangling pin on`
221			`block:`
222			`str/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:.`
223
224			`Section 3 - Informational`
225			`-------------------------`
226			`INFO:Security:54 - 'xc3s1000' is a WebPack part.`
227			`INFO:MapLib:562 - No environment variables are currently set.`
228			`INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:`
229			`0.000 to 85.000 Celsius)`
230			`INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to`
231			`1.260 Volts)`
232			`INFO:Pack:1650 - Map created a placed design.`
233			`INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance`
234			`with the CLKFX and CLKFX180 outputs of the DCM comp clockdll/DCM_INST,`
235			`consult the device Interactive Data Sheet.`
236
237			`Section 4 - Removed Logic Summary`
238			`---------------------------------`
239			`4 block(s) optimized away`
240
241			`Section 5 - Removed Logic`
242			`-------------------------`
243
244			`Optimized Block(s):`
245			`TYPE BLOCK`
246			`GND XST_GND`
247			`VCC XST_VCC`
248			`GND mem/ram/XST_GND`
249			`VCC mem/ram/XST_VCC`
250
251			`To enable printing of redundant blocks removed and signals merged, set the`
252			`detailed map report option and rerun map.`
253
254			`Section 6 - IOB Properties`
255			`--------------------------`
256
257			`+---------------------------------------------------------------------------------------------------------------------------------------------------------+`
258			`\| IOB Name \| Type \| Direction \| IO Standard \| Diff \| Drive \| Slew \| Reg (s) \| Resistor \| IOB \|`
259			`\| \| \| \| \| Term \| Strength \| Rate \| \| \| Delay \|`
260			`+---------------------------------------------------------------------------------------------------------------------------------------------------------+`
261			`\| clk \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \| \|`
262			`\| ds0 \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
263			`\| ds1 \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
264			`\| ds2 \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
265			`\| ds3 \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
266			`\| extreset \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \| \|`
267			`\| led<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
268			`\| led<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
269			`\| led<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
270			`\| led<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
271			`\| led<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
272			`\| led<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
273			`\| led<6> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
274			`\| led<7> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
275			`\| pb0 \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \| \|`
276			`\| pb1 \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \| \|`
277			`\| pb2 \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \| \|`
278			`\| segA \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
279			`\| segB \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
280			`\| segC \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
281			`\| segD \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
282			`\| segE \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
283			`\| segF \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
284			`\| segG \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| FAST \| \| \| \|`
285			`\| sw<0> \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \| \|`
286			`\| sw<1> \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \| \|`
287			`\| sw<2> \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \| \|`
288			`\| sw<3> \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \| \|`
289			`\| sw<4> \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \| \|`
290			`\| sw<5> \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \| \|`
291			`\| sw<6> \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \| \|`
292			`\| sw<7> \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \| \|`
293			`+---------------------------------------------------------------------------------------------------------------------------------------------------------+`
294
295			`Section 7 - RPMs`
296			`----------------`
297
298			`Section 8 - Guide Report`
299			`------------------------`
300			`Guide not run on this design.`
301
302			`Section 9 - Area Group and Partition Summary`
303			`--------------------------------------------`
304
305			`Partition Implementation Status`
306			`-------------------------------`
307
308			`No Partitions were found in this design.`
309
310			`-------------------------------`
311
312			`Area Group Information`
313			`----------------------`
314
315			`No area groups were found in this design.`
316
317			`----------------------`
318
319			`Section 10 - Timing Report`
320			`--------------------------`
321			`A logic-level (pre-route) timing report can be generated by using Xilinx static`
322			`timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the`
323			`mapped NCD and PCF files. Please note that this timing report will be generated`
324			`using estimated delay information. For accurate numbers, please generate a`
325			`timing report with the post Place and Route NCD file.`
326
327			`For more information about the Timing Analyzer, consult the Xilinx Timing`
328			`Analyzer Reference Manual; for more information about TRCE, consult the Xilinx`
329			`Command Line Tools User Guide "TRACE" chapter.`
330
331			`Section 11 - Configuration String Details`
332			`-----------------------------------------`
333			`Use the "-detail" map option to print out Configuration Strings`
334
335			`Section 12 - Control Set Information`
336			`------------------------------------`
337			`No control set information for this architecture.`
338
339			`Section 13 - Utilization by Hierarchy`
340			`-------------------------------------`
341			`Use the "-detail" map option to print out the Utilization by Hierarchy section.`

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