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[/] [vtach/] [trunk/] [vtach_tb_beh.prj] - Blame information for rev 2

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verilog work "digitadd.v"
verilog work "io_output.v"
verilog work "io_input.v"
verilog work "bcdadd.v"
verilog work "memory.v"
verilog work "bcdincr.v"
verilog work "alu.v"
verilog work "vtach.v"
verilog work "vtach_tb.v"
verilog work "/opt/Xilinx/13.1/ISE_DS/ISE//verilog/src/glbl.v"

Line No.	Rev	Author	Line
1	2	wd5gnr	`verilog work "digitadd.v"`
2			`verilog work "io_output.v"`
3			`verilog work "io_input.v"`
4			`verilog work "bcdadd.v"`
5			`verilog work "memory.v"`
6			`verilog work "bcdincr.v"`
7			`verilog work "alu.v"`
8			`verilog work "vtach.v"`
9			`verilog work "vtach_tb.v"`
10			`verilog work "/opt/Xilinx/13.1/ISE_DS/ISE//verilog/src/glbl.v"`

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[/] [vtach/] [trunk/] [vtach_tb_beh.prj] - Blame information for rev 2