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[/] [warp/] [rtl/] [tmu_burst.v] - Blame information for rev 7

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1 7 lekernel 
/*
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 * Milkymist VJ SoC
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 * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
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 *
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 * This program is free and excepted software; you can use it, redistribute it
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 * and/or modify it under the terms of the Exception General Public License as
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 * published by the Exception License Foundation; either version 2 of the
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 * License, or (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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 * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more
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 * details.
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 *
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 * You should have received a copy of the Exception General Public License along
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 * with this project; if not, write to the Exception License Foundation.
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 */
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module tmu_burst #(
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        parameter fml_depth = 26
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) (
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        input sys_clk,
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        input sys_rst,
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        input flush,
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        output reg busy,
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        input pipe_stb_i,
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        output pipe_ack_o,
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        input [15:0] src_pixel_d,
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        input [fml_depth-1-1:0] dst_addr, /* in 16-bit words */
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        output reg pipe_stb_o,
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        input pipe_ack_i,
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        output reg [fml_depth-5-1:0] burst_addr, /* in 256-bit words */
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        /* 16-bit granularity selection that needs to be expanded
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         * to 8-bit granularity selection to drive the FML lines.
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         */
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        output reg [15:0] burst_sel,
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        output reg [255:0] burst_do
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);
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wire burst_hit = dst_addr[fml_depth-1-1:4] == burst_addr;
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/* Always memorize input in case we have to ack a cycle we cannot immediately handle */
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reg [15:0] src_pixel_d_r;
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reg [fml_depth-1-1:0] dst_addr_r;
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always @(posedge sys_clk) begin
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        if(pipe_stb_i & pipe_ack_o) begin
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                src_pixel_d_r <= src_pixel_d;
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                dst_addr_r <= dst_addr;
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        end
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end
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/* Write to the burst storage registers */
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reg clear_en;
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reg write_en;
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reg use_memorized;
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wire [15:0] src_pixel_d_mux = use_memorized ? src_pixel_d_r : src_pixel_d;
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wire [fml_depth-1-1:0] dst_addr_mux = use_memorized ? dst_addr_r : dst_addr;
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always @(posedge sys_clk) begin
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        if(sys_rst)
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                burst_sel = 16'd0;
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        else begin
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                if(clear_en)
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                        burst_sel = 16'd0;
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                if(write_en) begin
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                        burst_addr = dst_addr_mux[fml_depth-1-1:4]; /* update tag */
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                        case(dst_addr_mux[3:0]) /* unmask */
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                                4'd00: burst_sel = burst_sel | 16'h8000;
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                                4'd01: burst_sel = burst_sel | 16'h4000;
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                                4'd02: burst_sel = burst_sel | 16'h2000;
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                                4'd03: burst_sel = burst_sel | 16'h1000;
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                                4'd04: burst_sel = burst_sel | 16'h0800;
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                                4'd05: burst_sel = burst_sel | 16'h0400;
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                                4'd06: burst_sel = burst_sel | 16'h0200;
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                                4'd07: burst_sel = burst_sel | 16'h0100;
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                                4'd08: burst_sel = burst_sel | 16'h0080;
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                                4'd09: burst_sel = burst_sel | 16'h0040;
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                                4'd10: burst_sel = burst_sel | 16'h0020;
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                                4'd11: burst_sel = burst_sel | 16'h0010;
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                                4'd12: burst_sel = burst_sel | 16'h0008;
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                                4'd13: burst_sel = burst_sel | 16'h0004;
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                                4'd14: burst_sel = burst_sel | 16'h0002;
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                                4'd15: burst_sel = burst_sel | 16'h0001;
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                        endcase
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                        case(dst_addr_mux[3:0]) /* register data */
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                                4'd00: burst_do[255:240] = src_pixel_d_mux;
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                                4'd01: burst_do[239:224] = src_pixel_d_mux;
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                                4'd02: burst_do[223:208] = src_pixel_d_mux;
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                                4'd03: burst_do[207:192] = src_pixel_d_mux;
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                                4'd04: burst_do[191:176] = src_pixel_d_mux;
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                                4'd05: burst_do[175:160] = src_pixel_d_mux;
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                                4'd06: burst_do[159:144] = src_pixel_d_mux;
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                                4'd07: burst_do[143:128] = src_pixel_d_mux;
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                                4'd08: burst_do[127:112] = src_pixel_d_mux;
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                                4'd09: burst_do[111: 96] = src_pixel_d_mux;
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                                4'd10: burst_do[ 95: 80] = src_pixel_d_mux;
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                                4'd11: burst_do[ 79: 64] = src_pixel_d_mux;
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                                4'd12: burst_do[ 63: 48] = src_pixel_d_mux;
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                                4'd13: burst_do[ 47: 32] = src_pixel_d_mux;
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                                4'd14: burst_do[ 31: 16] = src_pixel_d_mux;
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                                4'd15: burst_do[ 15:  0] = src_pixel_d_mux;
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                        endcase
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                end
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        end
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end
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wire empty = (burst_sel == 16'd0);
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reg state;
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reg next_state;
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parameter RUNNING       = 1'b0;
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parameter DOWNSTREAM    = 1'b1;
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always @(posedge sys_clk) begin
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        if(sys_rst)
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                state <= RUNNING;
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        else
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                state <= next_state;
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end
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/*
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 * generate pipe_ack_o using an assign statement to work around a bug in CVER
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 */
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assign pipe_ack_o = (state == RUNNING) & (~flush | empty);
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always @(*) begin
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        next_state = state;
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        busy = 1'b1;
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        // CVER WA (see above) pipe_ack_o = 1'b0;
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        pipe_stb_o = 1'b0;
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        write_en = 1'b0;
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        clear_en = 1'b0;
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        use_memorized = 1'b0;
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        case(state)
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                RUNNING: begin
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                        busy = 1'b0;
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                        if(flush & ~empty)
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                                next_state = DOWNSTREAM;
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                        else begin
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                                // CVER WA (see above) pipe_ack_o = 1'b1;
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                                if(pipe_stb_i) begin
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                                        if(burst_hit | empty)
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                                                write_en = 1'b1;
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                                        else
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                                                next_state = DOWNSTREAM;
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                                end
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                        end
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                end
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                DOWNSTREAM: begin
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                        pipe_stb_o = 1'b1;
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                        use_memorized = 1'b1;
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                        if(pipe_ack_i) begin
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                                clear_en = 1'b1;
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                                write_en = 1'b1;
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                                next_state = RUNNING;
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                        end
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                end
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        endcase
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end
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endmodule

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