URL https://opencores.org/ocsvn/wb2axi4/wb2axi4/trunk

Subversion Repositories wb2axi4

[/] [wb2axi4/] [trunk/] [rtl/] [ifaces/] [axi_if.sv] - Blame information for rev 3

Details | Compare with Previous | View Log


interface axi_if
  #(AXI_ID_W               = 8,
    AXI_ADDR_W             = 32,
    AXI_DATA_W             = 32,
    AXI_PROT_W             = 3,
    AXI_STB_W              = 4,
    AXI_LEN_W              = 4,
    AXI_SIZE_W             = 3,
    AXI_BURST_W            = 2,
    AXI_LOCK_W             = 2,
    AXI_CACHE_W            = 4,
    AXI_RESP_W             = 2
  )
  ();
 
  //Write control channel signals
  logic [AXI_ID_W       - 1:0]  AWID    ;
  logic [AXI_ADDR_W     - 1:0]  AWADDR  ;
  logic [AXI_LEN_W      - 1:0]  AWLEN   ;
  logic [AXI_SIZE_W     - 1:0]  AWSIZE  ;
  logic [AXI_BURST_W    - 1:0]  AWBURST ;
  logic [AXI_LOCK_W     - 1:0]  AWLOCK  ;
  logic [AXI_CACHE_W    - 1:0]  AWCACHE ;
  logic [AXI_PROT_W     - 1:0]  AWPROT  ;
  logic                         AWVALID ;
  logic                         AWREADY ;
  //write data channel signals
  logic [AXI_ID_W      - 1:0 ]  WID     ;
  logic [AXI_DATA_W    - 1:0]   WDATA   ;
  logic [AXI_STB_W     - 1:0]   WSTRB   ;
  logic                         WLAST   ;
  logic                         WVALID  ;
  logic                         WREADY  ;
  //write response channel
  logic [AXI_ID_W       - 1:0]  BID     ;
  logic [AXI_RESP_W     - 1:0]  BRESP   ;
  logic                         BVALID  ;
  logic                         BREADY  ;
  //Read control channel signals
  logic [AXI_ID_W        - 1:0] ARID    ;
  logic [AXI_ADDR_W      - 1:0] ARADDR  ;
  logic [AXI_LEN_W       - 1:0] ARLEN   ;
  logic [AXI_SIZE_W      - 1:0] ARSIZE  ;
  logic [AXI_BURST_W     - 1:0] ARBURST ;
  logic [AXI_LOCK_W      - 1:0] ARLOCK  ;
  logic [AXI_CACHE_W     - 1:0] ARCACHE ;
  logic [AXI_PROT_W      - 1:0] ARPROT  ;
  logic                         ARVALID ;
  logic                         ARREADY ;
  //Read data channel signals
  logic [AXI_ID_W       - 1:0]  RID     ;
  logic [AXI_DATA_W     - 1:0]  RDATA   ;
  logic [AXI_RESP_W     - 1:0]  RRESP   ;
  logic                         RLAST   ;
  logic                         RVALID  ;
  logic                         RREADY  ;
 
modport initiator (
  //Write control channel signals
  output AWID    ,
  output AWADDR  ,
  output AWLEN   ,
  output AWSIZE  ,
  output AWBURST ,
  output AWLOCK  ,
  output AWCACHE ,
  output AWPROT  ,
  output AWVALID ,
  input  AWREADY ,
  //write data channel signals
  output WID     ,
  output WDATA   ,
  output WSTRB   ,
  output WLAST   ,
  output WVALID  ,
  input  WREADY  ,
  //write response channel
  input  BID     ,
  input  BRESP   ,
  input  BVALID  ,
  output BREADY  ,
  //Read control channel signals
  output ARID    ,
  output ARADDR  ,
  output ARLEN   ,
  output ARSIZE  ,
  output ARBURST ,
  output ARLOCK  ,
  output ARCACHE ,
  output ARPROT  ,
  output ARVALID ,
  input  ARREADY ,
  //Read data channel signals
  input  RID     ,
  input  RDATA   ,
  input  RRESP   ,
  input  RLAST   ,
  input  RVALID  ,
  output RREADY
);
 
modport target (
  //Write control channel signals
  input  AWID    ,
  input  AWADDR  ,
  input  AWLEN   ,
  input  AWSIZE  ,
  input  AWBURST ,
  input  AWLOCK  ,
  input  AWCACHE ,
  input  AWPROT  ,
  input  AWVALID ,
  output AWREADY ,
  //write data channel signals
  input  WID     ,
  input  WDATA   ,
  input  WSTRB   ,
  input  WLAST   ,
  input  WVALID  ,
  output WREADY  ,
  //write response channel
  output BID     ,
  output BRESP   ,
  output BVALID  ,
  input  BREADY  ,
  //Read control channel signals
  input  ARID    ,
  input  ARADDR  ,
  input  ARLEN   ,
  input  ARSIZE  ,
  input  ARBURST ,
  input  ARLOCK  ,
  input  ARCACHE ,
  input  ARPROT  ,
  input  ARVALID ,
  output ARREADY ,
  //Read data channel signals
  output RID     ,
  output RDATA   ,
  output RRESP   ,
  output RLAST   ,
  output RVALID  ,
  input  RREADY
);
 
endinterface
 

Line No.	Rev	Author	Line
1	2	alzhang	`interface axi_if`
2	3	alzhang	`#(AXI_ID_W = 8,`
3			`AXI_ADDR_W = 32,`
4			`AXI_DATA_W = 32,`
5			`AXI_PROT_W = 3,`
6			`AXI_STB_W = 4,`
7			`AXI_LEN_W = 4,`
8			`AXI_SIZE_W = 3,`
9			`AXI_BURST_W = 2,`
10			`AXI_LOCK_W = 2,`
11			`AXI_CACHE_W = 4,`
12			`AXI_RESP_W = 2`
13	2	alzhang	`)`
14			`();`
15
16			`//Write control channel signals`
17	3	alzhang	`logic [AXI_ID_W - 1:0] AWID ;`
18			`logic [AXI_ADDR_W - 1:0] AWADDR ;`
19			`logic [AXI_LEN_W - 1:0] AWLEN ;`
20			`logic [AXI_SIZE_W - 1:0] AWSIZE ;`
21			`logic [AXI_BURST_W - 1:0] AWBURST ;`
22			`logic [AXI_LOCK_W - 1:0] AWLOCK ;`
23			`logic [AXI_CACHE_W - 1:0] AWCACHE ;`
24			`logic [AXI_PROT_W - 1:0] AWPROT ;`
25			`logic AWVALID ;`
26			`logic AWREADY ;`
27	2	alzhang	`//write data channel signals`
28	3	alzhang	`logic [AXI_ID_W - 1:0 ] WID ;`
29			`logic [AXI_DATA_W - 1:0] WDATA ;`
30			`logic [AXI_STB_W - 1:0] WSTRB ;`
31			`logic WLAST ;`
32			`logic WVALID ;`
33			`logic WREADY ;`
34	2	alzhang	`//write response channel`
35	3	alzhang	`logic [AXI_ID_W - 1:0] BID ;`
36			`logic [AXI_RESP_W - 1:0] BRESP ;`
37			`logic BVALID ;`
38			`logic BREADY ;`
39	2	alzhang	`//Read control channel signals`
40	3	alzhang	`logic [AXI_ID_W - 1:0] ARID ;`
41			`logic [AXI_ADDR_W - 1:0] ARADDR ;`
42	2	alzhang	`logic [AXI_LEN_W - 1:0] ARLEN ;`
43	3	alzhang	`logic [AXI_SIZE_W - 1:0] ARSIZE ;`
44			`logic [AXI_BURST_W - 1:0] ARBURST ;`
45			`logic [AXI_LOCK_W - 1:0] ARLOCK ;`
46			`logic [AXI_CACHE_W - 1:0] ARCACHE ;`
47			`logic [AXI_PROT_W - 1:0] ARPROT ;`
48	2	alzhang	`logic ARVALID ;`
49			`logic ARREADY ;`
50			`//Read data channel signals`
51	3	alzhang	`logic [AXI_ID_W - 1:0] RID ;`
52			`logic [AXI_DATA_W - 1:0] RDATA ;`
53			`logic [AXI_RESP_W - 1:0] RRESP ;`
54			`logic RLAST ;`
55			`logic RVALID ;`
56			`logic RREADY ;`
57	2	alzhang
58			`modport initiator (`
59			`//Write control channel signals`
60			`output AWID ,`
61			`output AWADDR ,`
62			`output AWLEN ,`
63			`output AWSIZE ,`
64			`output AWBURST ,`
65			`output AWLOCK ,`
66			`output AWCACHE ,`
67			`output AWPROT ,`
68			`output AWVALID ,`
69			`input AWREADY ,`
70			`//write data channel signals`
71			`output WID ,`
72			`output WDATA ,`
73			`output WSTRB ,`
74			`output WLAST ,`
75			`output WVALID ,`
76			`input WREADY ,`
77			`//write response channel`
78			`input BID ,`
79			`input BRESP ,`
80			`input BVALID ,`
81			`output BREADY ,`
82			`//Read control channel signals`
83			`output ARID ,`
84			`output ARADDR ,`
85			`output ARLEN ,`
86			`output ARSIZE ,`
87			`output ARBURST ,`
88			`output ARLOCK ,`
89			`output ARCACHE ,`
90			`output ARPROT ,`
91			`output ARVALID ,`
92			`input ARREADY ,`
93			`//Read data channel signals`
94			`input RID ,`
95			`input RDATA ,`
96			`input RRESP ,`
97			`input RLAST ,`
98			`input RVALID ,`
99			`output RREADY`
100			`);`
101
102			`modport target (`
103			`//Write control channel signals`
104			`input AWID ,`
105			`input AWADDR ,`
106			`input AWLEN ,`
107			`input AWSIZE ,`
108			`input AWBURST ,`
109			`input AWLOCK ,`
110			`input AWCACHE ,`
111			`input AWPROT ,`
112			`input AWVALID ,`
113			`output AWREADY ,`
114			`//write data channel signals`
115			`input WID ,`
116			`input WDATA ,`
117			`input WSTRB ,`
118			`input WLAST ,`
119			`input WVALID ,`
120			`output WREADY ,`
121			`//write response channel`
122			`output BID ,`
123			`output BRESP ,`
124			`output BVALID ,`
125			`input BREADY ,`
126			`//Read control channel signals`
127			`input ARID ,`
128			`input ARADDR ,`
129			`input ARLEN ,`
130			`input ARSIZE ,`
131			`input ARBURST ,`
132			`input ARLOCK ,`
133			`input ARCACHE ,`
134			`input ARPROT ,`
135			`input ARVALID ,`
136			`output ARREADY ,`
137			`//Read data channel signals`
138			`output RID ,`
139			`output RDATA ,`
140			`output RRESP ,`
141			`output RLAST ,`
142			`output RVALID ,`
143			`input RREADY`
144			`);`
145
146			`endinterface`
147

Browse

Tools

Subversion Repositories wb2axi4

[/] [wb2axi4/] [trunk/] [rtl/] [ifaces/] [axi_if.sv] - Blame information for rev 3