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alzhang |
`include "wb2axi_parameters.vh"
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module tb;
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reg axi_clk;
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reg wb_clk;
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reg resetn;
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axi_if #(
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.AXI_ID_W (`WB2AXI_AXI_ID_W ),
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.AXI_ADDR_W (`WB2AXI_AXI_ADDR_W ),
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.AXI_DATA_W (`WB2AXI_AXI_DATA_W ),
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.AXI_PROT_W (`WB2AXI_AXI_PROT_W ),
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.AXI_STB_W (`WB2AXI_AXI_STB_W ),
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.AXI_LEN_W (`WB2AXI_AXI_LEN_W ),
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.AXI_SIZE_W (`WB2AXI_AXI_SIZE_W ),
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.AXI_BURST_W (`WB2AXI_AXI_BURST_W ),
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.AXI_LOCK_W (`WB2AXI_AXI_LOCK_W ),
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.AXI_CACHE_W (`WB2AXI_AXI_CACHE_W ),
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.AXI_RESP_W (`WB2AXI_AXI_RESP_W )
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) axi_if_m();
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wishbone_if #(
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.WB_ADR_WIDTH(`WB2AXI_WB_ADR_W) ,
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.WB_BTE_WIDTH(`WB2AXI_WB_BTE_W) ,
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.WB_CTI_WIDTH(`WB2AXI_WB_CTI_W) ,
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.WB_DAT_WIDTH(`WB2AXI_WB_DAT_W) ,
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.WB_TGA_WIDTH(`WB2AXI_WB_TGA_W) ,
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.WB_TGD_WIDTH(`WB2AXI_WB_TGD_W) ,
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.WB_TGC_WIDTH(`WB2AXI_WB_TGC_W) ,
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.WB_SEL_WIDTH(`WB2AXI_WB_SEL_W)
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) wb_if_s();
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assign wb_if_s.ACK = 1'b1;
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axi_master_model# (
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.AXI_ID_W (`WB2AXI_AXI_ID_W ),
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.AXI_ADDR_W (`WB2AXI_AXI_ADDR_W ),
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.AXI_DATA_W (`WB2AXI_AXI_DATA_W ),
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.AXI_PROT_W (`WB2AXI_AXI_PROT_W ),
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.AXI_STB_W (`WB2AXI_AXI_STB_W ),
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.AXI_LEN_W (`WB2AXI_AXI_LEN_W ),
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.AXI_SIZE_W (`WB2AXI_AXI_SIZE_W ),
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.AXI_BURST_W (`WB2AXI_AXI_BURST_W ),
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.AXI_LOCK_W (`WB2AXI_AXI_LOCK_W ),
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.AXI_CACHE_W (`WB2AXI_AXI_CACHE_W ),
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.AXI_RESP_W (`WB2AXI_AXI_RESP_W )
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)I_AXIM (
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.axi_clk (axi_clk ),
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.axi_resetn (resetn ),
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.AWID (axi_if_m.AWID ),
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.AWADDR (axi_if_m.AWADDR ),
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.AWLEN (axi_if_m.AWLEN ),
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.AWSIZE (axi_if_m.AWSIZE ),
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.AWBURST (axi_if_m.AWBURST),
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.AWLOCK (axi_if_m.AWLOCK ),
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.AWCACHE (axi_if_m.AWCACHE),
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.AWPROT (axi_if_m.AWPROT ),
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.AWVALID (axi_if_m.AWVALID),
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.AWREADY (axi_if_m.AWREADY),
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.WID (axi_if_m.WID ),
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.WDATA (axi_if_m.WDATA ),
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.WSTRB (axi_if_m.WSTRB ),
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.WLAST (axi_if_m.WLAST ),
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.WVALID (axi_if_m.WVALID ),
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.WREADY (axi_if_m.WREADY ),
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.BID (axi_if_m.BID ),
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.BRESP (axi_if_m.BRESP ),
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.BVALID (axi_if_m.BVALID ),
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.BREADY (axi_if_m.BREADY ),
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.ARID (axi_if_m.ARID ),
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.ARADDR (axi_if_m.ARADDR ),
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.ARLEN (axi_if_m.ARLEN ),
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.ARSIZE (axi_if_m.ARSIZE ),
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.ARBURST (axi_if_m.ARBURST),
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.ARLOCK (axi_if_m.ARLOCK ),
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.ARCACHE (axi_if_m.ARCACHE),
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.ARPROT (axi_if_m.ARPROT ),
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.ARVALID (axi_if_m.ARVALID),
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.ARREADY (axi_if_m.ARREADY),
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.RID (axi_if_m.RID ),
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.RDATA (axi_if_m.RDATA ),
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.RRESP (axi_if_m.RRESP ),
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.RLAST (axi_if_m.RLAST ),
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.RVALID (axi_if_m.RVALID ),
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.RREADY (axi_if_m.RREADY )
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);
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axi2wb #(
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.AXI_ID_W (`WB2AXI_AXI_ID_W ),
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.AXI_ADDR_W (`WB2AXI_AXI_ADDR_W ),
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.AXI_DATA_W (`WB2AXI_AXI_DATA_W ),
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.AXI_PROT_W (`WB2AXI_AXI_PROT_W ),
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.AXI_STB_W (`WB2AXI_AXI_STB_W ),
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.AXI_LEN_W (`WB2AXI_AXI_LEN_W ),
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.AXI_SIZE_W (`WB2AXI_AXI_SIZE_W ),
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.AXI_BURST_W (`WB2AXI_AXI_BURST_W ),
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.AXI_LOCK_W (`WB2AXI_AXI_LOCK_W ),
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.AXI_CACHE_W (`WB2AXI_AXI_CACHE_W ),
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.AXI_RESP_W (`WB2AXI_AXI_RESP_W ),
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.FIFO_ADDR_DEPTH_W(`WB2AXI_FIFO_ADDR_DEPTH_W),
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.FIFO_DATA_DEPTH_W(`WB2AXI_FIFO_DATA_DEPTH_W),
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.WB_ADR_W (`WB2AXI_WB_ADR_W ),
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.WB_DAT_W (`WB2AXI_WB_DAT_W ),
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.WB_TGA_W (`WB2AXI_WB_TGA_W ),
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.WB_TGD_W (`WB2AXI_WB_TGD_W ),
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.WB_TGC_W (`WB2AXI_WB_TGC_W ),
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.WB_SEL_W (`WB2AXI_WB_SEL_W ),
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.WB_CTI_W (`WB2AXI_WB_CTI_W ),
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.WB_BTE_W (`WB2AXI_WB_BTE_W )
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) I_AXI2WB (
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.axi_clk (axi_clk ),
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.wb_clk (wb_clk ),
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.axi_resetn(resetn ),
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.wb_resetn (resetn ),
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.ENABLE (1'b1 ),
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.AXI_IF (axi_if_m),
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.WB_TX_IF (wb_if_s )
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);
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initial begin
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wb_clk = 1'b1;
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axi_clk= 1'b1;
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resetn = 1'b1;
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#10;
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resetn = 1'b0;
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#100;
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$display ("Resetn is done");
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resetn = 1'b1;
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#20000;
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$display ("Simulation is done");
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$finish;
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end
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always begin
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#2;
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axi_clk = ~axi_clk;
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end
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always begin
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#5 wb_clk = ~wb_clk;
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end
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initial begin
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$fsdbDumpfile("./test_wb2axi.fsdb");
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$fsdbDumpvars(0, tb);
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end
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endmodule
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