URL https://opencores.org/ocsvn/wb_async_mem_bridge/wb_async_mem_bridge/trunk

Subversion Repositories wb_async_mem_bridge

[/] [wb_async_mem_bridge/] [trunk/] [sim/] [tests/] [debug/] [tb_dut.v] - Blame information for rev 6

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// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module tb_dut(
                input tb_clk,
                input tb_rst
              );
 
 
  // --------------------------------------------------------------------
  //  async_mem_master
  wire [31:0] mem_d;
  wire [31:0] mem_a;
  wire        mem_oe_n;
  wire [3:0]  mem_bls_n;
  wire        mem_we_n;
  wire        mem_cs_n;
 
  async_mem_master
    async_mem(
      .mem_d(mem_d),
      .mem_a(mem_a),
      .mem_oe_n(mem_oe_n),
      .mem_bls_n(mem_bls_n),
      .mem_we_n(mem_we_n),
      .mem_cs_n(mem_cs_n),
 
      .tb_clk(tb_clk),
      .tb_rst(tb_rst)
    );
 
 
 
  // --------------------------------------------------------------------
  //  wb_async_mem_bridge
    wire [31:0]   wb_data_i;
    wire [31:0]   wb_data_o;
    wire [31:0]   wb_addr_o;
    wire [3:0]    wb_sel_o;
    wire          wb_we_o;
    wire          wb_cyc_o;
    wire          wb_stb_o;
    wire          wb_ack_i;
    wire          wb_err_i;
    wire          wb_rty_i;
 
  wb_async_mem_bridge
    i_wb_async_mem_bridge(
      .wb_data_i(wb_data_i),
      .wb_data_o(wb_data_o),
      .wb_addr_o(wb_addr_o),
      .wb_sel_o(wb_sel_o),
      .wb_we_o(wb_we_o),
      .wb_cyc_o(wb_cyc_o),
      .wb_stb_o(wb_stb_o),
      .wb_ack_i(wb_ack_i),
      .wb_err_i(wb_err_i),
      .wb_rty_i(wb_rty_i),
 
      .mem_d(mem_d),
      .mem_a(mem_a),
      .mem_oe_n(mem_oe_n),
      .mem_bls_n(mem_bls_n),
      .mem_we_n(mem_we_n),
      .mem_cs_n(mem_cs_n),
 
      .wb_clk_i(tb_clk),
      .wb_rst_i(tb_rst)
  );
 
 
 
  // --------------------------------------------------------------------
  //  wb_slave_model
  wb_slave_model #(.DWIDTH(32), .AWIDTH(8), .ACK_DELAY(0), .SLAVE_RAM_INIT("wb_slave_32_bit.txt") )
    i_wb_slave_model(
      .clk_i(tb_clk),
      .rst_i(tb_rst),
      .dat_o(wb_data_i),
      .dat_i(wb_data_o),
      .adr_i(wb_addr_o),
      .cyc_i(wb_cyc_o),
      .stb_i(wb_stb_o),
      .we_i(wb_we_o),
      .sel_i(wb_sel_o),
      .ack_o(wb_ack_i),
      .err_o(wb_err_i),
      .rty_o(wb_rty_i)
    );
 
 
 
endmodule
 
 

Line No.	Rev	Author	Line
1	6	qaztronic	`// --------------------------------------------------------------------`
2			`//`
3			`// --------------------------------------------------------------------`
4
5			`timescale 1ns/10ps
6
7
8			`module tb_dut(`
9			`input tb_clk,`
10			`input tb_rst`
11			`);`
12
13
14			`// --------------------------------------------------------------------`
15			`// async_mem_master`
16			`wire [31:0] mem_d;`
17			`wire [31:0] mem_a;`
18			`wire mem_oe_n;`
19			`wire [3:0] mem_bls_n;`
20			`wire mem_we_n;`
21			`wire mem_cs_n;`
22
23			`async_mem_master`
24			`async_mem(`
25			`.mem_d(mem_d),`
26			`.mem_a(mem_a),`
27			`.mem_oe_n(mem_oe_n),`
28			`.mem_bls_n(mem_bls_n),`
29			`.mem_we_n(mem_we_n),`
30			`.mem_cs_n(mem_cs_n),`
31
32			`.tb_clk(tb_clk),`
33			`.tb_rst(tb_rst)`
34			`);`
35
36
37
38			`// --------------------------------------------------------------------`
39			`// wb_async_mem_bridge`
40			`wire [31:0] wb_data_i;`
41			`wire [31:0] wb_data_o;`
42			`wire [31:0] wb_addr_o;`
43			`wire [3:0] wb_sel_o;`
44			`wire wb_we_o;`
45			`wire wb_cyc_o;`
46			`wire wb_stb_o;`
47			`wire wb_ack_i;`
48			`wire wb_err_i;`
49			`wire wb_rty_i;`
50
51			`wb_async_mem_bridge`
52			`i_wb_async_mem_bridge(`
53			`.wb_data_i(wb_data_i),`
54			`.wb_data_o(wb_data_o),`
55			`.wb_addr_o(wb_addr_o),`
56			`.wb_sel_o(wb_sel_o),`
57			`.wb_we_o(wb_we_o),`
58			`.wb_cyc_o(wb_cyc_o),`
59			`.wb_stb_o(wb_stb_o),`
60			`.wb_ack_i(wb_ack_i),`
61			`.wb_err_i(wb_err_i),`
62			`.wb_rty_i(wb_rty_i),`
63
64			`.mem_d(mem_d),`
65			`.mem_a(mem_a),`
66			`.mem_oe_n(mem_oe_n),`
67			`.mem_bls_n(mem_bls_n),`
68			`.mem_we_n(mem_we_n),`
69			`.mem_cs_n(mem_cs_n),`
70
71			`.wb_clk_i(tb_clk),`
72			`.wb_rst_i(tb_rst)`
73			`);`
74
75
76
77			`// --------------------------------------------------------------------`
78			`// wb_slave_model`
79			`wb_slave_model #(.DWIDTH(32), .AWIDTH(8), .ACK_DELAY(0), .SLAVE_RAM_INIT("wb_slave_32_bit.txt") )`
80			`i_wb_slave_model(`
81			`.clk_i(tb_clk),`
82			`.rst_i(tb_rst),`
83			`.dat_o(wb_data_i),`
84			`.dat_i(wb_data_o),`
85			`.adr_i(wb_addr_o),`
86			`.cyc_i(wb_cyc_o),`
87			`.stb_i(wb_stb_o),`
88			`.we_i(wb_we_o),`
89			`.sel_i(wb_sel_o),`
90			`.ack_o(wb_ack_i),`
91			`.err_o(wb_err_i),`
92			`.rty_o(wb_rty_i)`
93			`);`
94
95
96
97			`endmodule`
98
99

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[/] [wb_async_mem_bridge/] [trunk/] [sim/] [tests/] [debug/] [tb_dut.v] - Blame information for rev 6