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Subversion Repositories wb_async_mem_bridge

[/] [wb_async_mem_bridge/] [trunk/] [src/] [sync.v] - Blame information for rev 6

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1 6 qaztronic 
// --------------------------------------------------------------------
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//
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// --------------------------------------------------------------------
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`include "timescale.v"
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module sync (
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              input async_sig,
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              output sync_out,
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              input clk
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            );
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  reg [1:2] resync;
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  always @(posedge clk)
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  begin
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    // update history shifter.
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    resync <= {async_sig , resync[1]};
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  end
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  assign sync_out = resync[2];
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endmodule
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