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URL https://opencores.org/ocsvn/wb_async_mem_bridge/wb_async_mem_bridge/trunk

Subversion Repositories wb_async_mem_bridge

[/] [wb_async_mem_bridge/] [trunk/] [src/] [wb_async_mem_bridge.v] - Blame information for rev 2

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1 2 qaztronic 
// --------------------------------------------------------------------
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//
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// --------------------------------------------------------------------
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`include "timescale.v"
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module
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  wb_async_mem_bridge
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  #(
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    parameter DW = 32,
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    parameter AW = 32
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  )
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  (
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    input   [(DW-1):0]  wb_data_i,
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    output  [(DW-1):0]  wb_data_o,
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    output  [(AW-1):0]  wb_addr_o,
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    output  [3:0]       wb_sel_o,
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    output              wb_we_o,
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    output              wb_cyc_o,
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    output              wb_stb_o,
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    input               wb_ack_i,
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    input               wb_err_i,
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    input               wb_rty_i,
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    inout   [(DW-1):0]  mem_d,
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    input   [(AW-1):0]  mem_a,
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    input               mem_oe_n,
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    input   [3:0]       mem_bls_n,
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    input               mem_we_n,
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    input               mem_cs_n,
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    input               wb_clk_i,
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    input               wb_rst_i
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  );
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// --------------------------------------------------------------------
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//  sync data & bls
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  wire [(DW-1):0] sync_mem_d;
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  wire [(AW-1):0] sync_mem_a;
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  wire [3:0] sync_mem_bls_n;
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  genvar i;
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  generate
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    for( i = 0; i < DW; i = i + 1 )
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      begin: sync_data_loop
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        sync i_sync( .async_sig(mem_d[i]), .sync_out(sync_mem_d[i]), .clk(wb_clk_i) );
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      end
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  endgenerate
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  generate
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    for( i = 0; i < AW; i = i + 1 )
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      begin: sync_addr_loop
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        sync i_sync( .async_sig(mem_a[i]), .sync_out(sync_mem_a[i]), .clk(wb_clk_i) );
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      end
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  endgenerate
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  generate
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    for( i = 0; i < 4; i = i + 1 )
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      begin: sync_bls_loop
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        sync i_sync( .async_sig(mem_bls_n[i]), .sync_out(sync_mem_bls_n[i]), .clk(wb_clk_i) );
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      end
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  endgenerate
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// --------------------------------------------------------------------
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//  sync mem_cs_n & mem_oe_n & mem_we_n
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  wire sync_mem_oe_n, sync_mem_oe_n_rise, sync_mem_oe_n_fall;
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  wire sync_mem_cs_n;
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  wire sync_mem_we_n, sync_mem_we_n_rise, sync_mem_we_n_fall;
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  sync
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    (
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            .async_sig(),
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            .sync_out(),
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            .clk(wb_clk_i)
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          );
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  sync_edge_detect
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    i_sync_mem_oe_n(
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                    .async_sig(mem_oe_n),
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                    .sync_out(sync_mem_oe_n),
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                    .clk(wb_clk_i),
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                    .rise(sync_mem_oe_n_rise),
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                    .fall(sync_mem_oe_n_fall)
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                  );
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  sync
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    i_sync_mem_cs_n(
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            .async_sig(mem_cs_n),
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            .sync_out(sync_mem_cs_n),
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            .clk(wb_clk_i)
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          );
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  sync_edge_detect
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    i_sync_mem_we_n(
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                    .async_sig(mem_we_n),
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                    .sync_out(sync_mem_we_n),
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                    .clk(wb_clk_i),
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                    .rise(sync_mem_we_n_rise),
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                    .fall(sync_mem_we_n_fall)
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                  );
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// --------------------------------------------------------------------
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//  state machine
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  wb_async_mem_sm #( .DW(DW), .AW(AW) )
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    i_wb_async_mem_sm
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    (
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      .wb_data_i(wb_data_i),
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//       .wb_data_o(wb_data_o),
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      .wb_addr_i(wb_addr_o),
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//       .wb_sel_o(wb_sel_o),
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      .wb_we_o(wb_we_o),
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      .wb_cyc_o(wb_cyc_o),
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      .wb_stb_o(wb_stb_o),
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      .wb_ack_i(wb_ack_i),
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      .wb_err_i(wb_err_i),
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      .wb_rty_i(wb_rty_i),
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      .mem_d(sync_mem_d),
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      .mem_a(sync_mem_a),
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      .mem_oe_n(sync_mem_oe_n),
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      .mem_bls_n(sync_mem_bls_n),
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      .mem_we_n(sync_mem_we_n),
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      .mem_cs_n(sync_mem_cs_n),
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      .mem_we_n_fall(sync_mem_we_n_fall),
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      .mem_oe_n_fall(sync_mem_oe_n_fall),
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      .wb_clk_i(wb_clk_i),
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      .wb_rst_i(wb_rst_i)
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    );
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// --------------------------------------------------------------------
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//  wb_data_i flop
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  reg [(DW-1):0] wb_data_i_r;
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  always @(posedge wb_clk_i)
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    if(wb_ack_i)
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      wb_data_i_r <= wb_data_i;
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// --------------------------------------------------------------------
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//  wb_data_o flop
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  reg [(DW-1):0] wb_data_o_r;
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  always @(posedge wb_clk_i)
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    if(~sync_mem_we_n)
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      wb_data_o_r <= sync_mem_d;
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// --------------------------------------------------------------------
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//  outputs
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  assign mem_d = (~sync_mem_oe_n & ~sync_mem_cs_n ) ? wb_data_i_r : 'bz;
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  assign wb_addr_o = sync_mem_a;
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  assign wb_data_o = wb_data_o_r;
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  assign wb_sel_o = ~sync_mem_bls_n;
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endmodule
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