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[/] [wb_async_mem_bridge/] [trunk/] [src/] [wb_async_mem_sm.v] - Blame information for rev 2

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// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module
  wb_async_mem_sm
  #(
    parameter DW = 32,
    parameter AW = 32
  )
  (
    input   [(DW-1):0]  wb_data_i,
    output  [(DW-1):0]  wb_data_o,
    input   [(AW-1):0]  wb_addr_i,
    output  [3:0]       wb_sel_o,
    output              wb_we_o,
    output              wb_cyc_o,
    output              wb_stb_o,
    input               wb_ack_i,
    input               wb_err_i,
    input               wb_rty_i,
 
    input   [(DW-1):0]  mem_d,
    input   [(AW-1):0]  mem_a,
    input               mem_oe_n,
    input   [3:0]       mem_bls_n,
    input               mem_we_n,
    input               mem_cs_n,
 
    input               mem_we_n_fall,
    input               mem_oe_n_fall,
 
    output  [5:0]       dbg_state,
 
    input               wb_clk_i,
    input               wb_rst_i
  );
 
 
  // --------------------------------------------------------------------
  //  wires
  wire address_change;
 
 
  // --------------------------------------------------------------------
  //  state machine
 
  localparam   STATE_IDLE     = 6'b000001;
  localparam   STATE_WE       = 6'b000010;
  localparam   STATE_OE       = 6'b000100;
  localparam   STATE_DONE     = 6'b001000;
  localparam   STATE_ERROR    = 6'b010000;
  localparam   STATE_GLITCH   = 6'b100000;
 
  reg [5:0] state;
  reg [5:0] next_state;
 
  always @(posedge wb_clk_i or posedge wb_rst_i)
    if(wb_rst_i)
      state <= STATE_IDLE;
    else
      state <= next_state;
 
  always @(*)
    case( state )
      STATE_IDLE:       if( (mem_oe_n & mem_we_n) | mem_cs_n )
                          next_state = STATE_IDLE;
                        else
                          if( ~mem_oe_n & ~mem_we_n )
                            next_state = STATE_ERROR;
                          else
                            if( ~mem_we_n )
                              next_state = STATE_WE;
                            else
                              next_state = STATE_OE;
 
      STATE_WE:         if( mem_we_n | mem_cs_n )
                          next_state = STATE_ERROR;
                        else
                          if( wb_ack_i )
                            next_state = STATE_DONE;
                          else
                            next_state = STATE_WE;
 
      STATE_OE:         if( mem_oe_n | mem_cs_n | address_change )
                          next_state = STATE_ERROR;
                        else
                          if( wb_ack_i )
                            next_state = STATE_DONE;
                          else
                            next_state = STATE_OE;
 
      STATE_DONE:       if( mem_cs_n )
                          next_state = STATE_IDLE;
                        else
                          if( mem_we_n_fall )
                            next_state = STATE_WE;
                          else if( mem_oe_n_fall )
                            next_state = STATE_OE;
                          else
                            next_state = STATE_DONE;
 
      STATE_ERROR:      next_state = STATE_IDLE;
 
      STATE_GLITCH:     next_state = STATE_IDLE;
 
      default:          next_state = STATE_GLITCH;
    endcase
 
 
// --------------------------------------------------------------------
//  wb_addr_i flop
  reg [(AW-1):0] wb_addr_i_r;
  assign address_change = (wb_addr_i != wb_addr_i_r);
 
  always @(posedge wb_clk_i)
    if( (state != STATE_DONE) | (state != STATE_OE) )
      wb_addr_i_r <= wb_addr_i;
 
 
// --------------------------------------------------------------------
//  outputs
  assign wb_cyc_o = (state == STATE_WE) | (state == STATE_OE);
  assign wb_stb_o = (state == STATE_WE) | (state == STATE_OE);
  assign wb_we_o  = (state == STATE_WE);
 
  assign dbg_state = state;
 
endmodule
 

Line No.	Rev	Author	Line
1	2	qaztronic	`// --------------------------------------------------------------------`
2			`//`
3			`// --------------------------------------------------------------------`
4
5			`include "timescale.v"
6
7
8			`module`
9			`wb_async_mem_sm`
10			`#(`
11			`parameter DW = 32,`
12			`parameter AW = 32`
13			`)`
14			`(`
15			`input [(DW-1):0] wb_data_i,`
16			`output [(DW-1):0] wb_data_o,`
17			`input [(AW-1):0] wb_addr_i,`
18			`output [3:0] wb_sel_o,`
19			`output wb_we_o,`
20			`output wb_cyc_o,`
21			`output wb_stb_o,`
22			`input wb_ack_i,`
23			`input wb_err_i,`
24			`input wb_rty_i,`
25
26			`input [(DW-1):0] mem_d,`
27			`input [(AW-1):0] mem_a,`
28			`input mem_oe_n,`
29			`input [3:0] mem_bls_n,`
30			`input mem_we_n,`
31			`input mem_cs_n,`
32
33			`input mem_we_n_fall,`
34			`input mem_oe_n_fall,`
35
36			`output [5:0] dbg_state,`
37
38			`input wb_clk_i,`
39			`input wb_rst_i`
40			`);`
41
42
43			`// --------------------------------------------------------------------`
44			`// wires`
45			`wire address_change;`
46
47
48			`// --------------------------------------------------------------------`
49			`// state machine`
50
51			`localparam STATE_IDLE = 6'b000001;`
52			`localparam STATE_WE = 6'b000010;`
53			`localparam STATE_OE = 6'b000100;`
54			`localparam STATE_DONE = 6'b001000;`
55			`localparam STATE_ERROR = 6'b010000;`
56			`localparam STATE_GLITCH = 6'b100000;`
57
58			`reg [5:0] state;`
59			`reg [5:0] next_state;`
60
61			`always @(posedge wb_clk_i or posedge wb_rst_i)`
62			`if(wb_rst_i)`
63			`state <= STATE_IDLE;`
64			`else`
65			`state <= next_state;`
66
67			`always @(*)`
68			`case( state )`
69			`STATE_IDLE: if( (mem_oe_n & mem_we_n) \| mem_cs_n )`
70			`next_state = STATE_IDLE;`
71			`else`
72			`if( ~mem_oe_n & ~mem_we_n )`
73			`next_state = STATE_ERROR;`
74			`else`
75			`if( ~mem_we_n )`
76			`next_state = STATE_WE;`
77			`else`
78			`next_state = STATE_OE;`
79
80			`STATE_WE: if( mem_we_n \| mem_cs_n )`
81			`next_state = STATE_ERROR;`
82			`else`
83			`if( wb_ack_i )`
84			`next_state = STATE_DONE;`
85			`else`
86			`next_state = STATE_WE;`
87
88			`STATE_OE: if( mem_oe_n \| mem_cs_n \| address_change )`
89			`next_state = STATE_ERROR;`
90			`else`
91			`if( wb_ack_i )`
92			`next_state = STATE_DONE;`
93			`else`
94			`next_state = STATE_OE;`
95
96			`STATE_DONE: if( mem_cs_n )`
97			`next_state = STATE_IDLE;`
98			`else`
99			`if( mem_we_n_fall )`
100			`next_state = STATE_WE;`
101			`else if( mem_oe_n_fall )`
102			`next_state = STATE_OE;`
103			`else`
104			`next_state = STATE_DONE;`
105
106			`STATE_ERROR: next_state = STATE_IDLE;`
107
108			`STATE_GLITCH: next_state = STATE_IDLE;`
109
110			`default: next_state = STATE_GLITCH;`
111			`endcase`
112
113
114			`// --------------------------------------------------------------------`
115			`// wb_addr_i flop`
116			`reg [(AW-1):0] wb_addr_i_r;`
117			`assign address_change = (wb_addr_i != wb_addr_i_r);`
118
119			`always @(posedge wb_clk_i)`
120			`if( (state != STATE_DONE) \| (state != STATE_OE) )`
121			`wb_addr_i_r <= wb_addr_i;`
122
123
124			`// --------------------------------------------------------------------`
125			`// outputs`
126			`assign wb_cyc_o = (state == STATE_WE) \| (state == STATE_OE);`
127			`assign wb_stb_o = (state == STATE_WE) \| (state == STATE_OE);`
128			`assign wb_we_o = (state == STATE_WE);`
129
130			`assign dbg_state = state;`
131
132			`endmodule`
133

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[/] [wb_async_mem_bridge/] [trunk/] [src/] [wb_async_mem_sm.v] - Blame information for rev 2