OpenCores
URL https://opencores.org/ocsvn/wb_lcd/wb_lcd/trunk
`timescale 1 ns / 1 ps module glbl (); wire GR; wire GSR; wire GTS; wire PRLD; endmodule

Subversion Repositories wb_lcd

[/] [wb_lcd/] [trunk/] [verilog/] [wb_lcd_ramless/] [boards/] [s3esk-mm_lcd/] [rtl/] [glbl.v] - Blame information for rev 2

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