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--
--  Technology mapping library. ALTERA edition.
--
--  (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
--  This code is distributed under the terms and conditions of the GNU General Public Lince.
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library exemplar;
--use exemplar.exemplar_1164.all;
library synopsys;
--use synopsys.std_logic_arith.all;
 
package body technology is
        function to_std_logic_vector(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
        begin
                return std_logic_arith.CONV_STD_LOGIC_VECTOR(arg,size);
        end;
 
        function to_integer(arg:std_logic_vector) return integer is
        begin
                return CONV_INTEGER(arg);
        end;
 
--      function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is
--      begin
--              return exemplar_1164."+"(op_l, op_r);
--      end;
--
--      function "-"(op_l, op_r: std_logic_vector) return std_logic_vector is
--      begin
--              return exemplar_1164."-"(op_l, op_r);
--      end;
--
--      function add_one(inp : std_logic_vector) return std_logic_vector is
--              variable one: std_logic_vector(inp'RANGE) := (others => '0');
--      begin
--              one(0) := '1';
--              return exemplar_1164."+"(inp,one);
--      end;
--
--      function sub_one(inp : std_logic_vector) return std_logic_vector is
--              variable minus_one: std_logic_vector(inp'RANGE) := (others => '1');
--      begin
--              return exemplar_1164."+"(inp,minus_one);
--      end;
 
        function is_zero(inp : std_logic_vector) return boolean is
                variable zero: std_logic_vector(inp'RANGE) := (others => '0');
        begin
                return (inp = zero);
        end;
 
        function sl(l: std_logic_vector; r: integer) return std_logic_vector is
        begin
                return exemplar_1164.sl(l,r);
        end;
 
        function sr(l: std_logic_vector; r: integer) return std_logic_vector is
        begin
                return sl(l,-r);
        end function;
 
        function max2(a : integer; b: integer) return integer is
        begin
                if (a > b) then return a; end if;
                return b;
        end;
 
        function min2(a : integer; b: integer) return integer is
        begin
                if (a < b) then return a; end if;
                return b;
        end;
 
        function log2(inp : integer) return integer is
        begin
                if (inp < 1) then return 0; end if;
                if (inp < 2) then return 0; end if;
                if (inp < 4) then return 1; end if;
                if (inp < 8) then return 2; end if;
                if (inp < 16) then return 3; end if;
                if (inp < 32) then return 4; end if;
                if (inp < 64) then return 5; end if;
                if (inp < 128) then return 6; end if;
                if (inp < 256) then return 7; end if;
                if (inp < 512) then return 8; end if;
                if (inp < 1024) then return 9; end if;
                if (inp < 2048) then return 10; end if;
                if (inp < 4096) then return 11; end if;
                if (inp < 8192) then return 12; end if;
                if (inp < 16384) then return 13; end if;
                if (inp < 32768) then return 14; end if;
                if (inp < 65536) then return 15; end if;
                return 16;
        end;
 
        function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer is
        begin
                if (in_bus = out_bus) then return 0; end if;
                if (in_bus < out_bus) then return -log2(out_bus/in_bus); end if;
                if (in_bus > out_bus) then return log2(in_bus/out_bus); end if;
        end;
 
        function size2bits(inp : integer) return integer is
        begin
                if (inp <= 1) then return 1; end if;
                if (inp <= 2) then return 1; end if;
                if (inp <= 4) then return 2; end if;
                if (inp <= 8) then return 3; end if;
                if (inp <= 16) then return 4; end if;
                if (inp <= 32) then return 5; end if;
                if (inp <= 64) then return 6; end if;
                if (inp <= 128) then return 7; end if;
                if (inp <= 256) then return 8; end if;
                if (inp <= 512) then return 9; end if;
                if (inp <= 1024) then return 10; end if;
                if (inp <= 2048) then return 11; end if;
                if (inp <= 4096) then return 12; end if;
                if (inp <= 8192) then return 13; end if;
                if (inp <= 16384) then return 14; end if;
                if (inp <= 32768) then return 15; end if;
                if (inp <= 65536) then return 16; end if;
                return 17;
        end;
 
        function equ(a : std_logic_vector; b : integer) return boolean is
                variable b_s : std_logic_vector(a'RANGE);
        begin
                b_s := to_std_logic_vector(b,a'HIGH+1);
                return (a = b_s);
        end;
 
end package body technology;
 
library IEEE;
use IEEE.std_logic_1164.all;
 
library altera;
use altera.maxplus2.all;
library alt_vtl;
use alt_vtl.all;
 
architecture altera of d_ff is
        signal clrn,prn: std_logic;
begin
        clrn <= not clr;
        prn <= not pre;
        ff: dffe port map (
                D => d,
                CLK => clk,
                ENA => ena,
                CLRN => clrn,
                PRN => prn,
                Q => q
        );
end altera;
 
library ieee;
use ieee.std_logic_1164.all;
library wb_tk;
use wb_tk.technology.all;
library lpm;
use lpm.all;
 
--  GENERIC usage
-------------------
--      default_out     : Not used in altera implementation
--      default_content : Not used in altera implementation
--      adr_width       : Correctly used
--      dat_width       : Correctly used
--      async_read      : Correctly used
architecture altera of dpmem is
        signal wren, rden: std_logic;
 
        COMPONENT lpm_ram_dp
                generic (LPM_WIDTH : positive;
                        LPM_WIDTHAD : positive;
                        LPM_NUMWORDS : natural := 0;
                        LPM_INDATA : string := "REGISTERED";
                        LPM_OUTDATA : string := "REGISTERED";
                        LPM_RDADDRESS_CONTROL : string := "REGISTERED";
                        LPM_WRADDRESS_CONTROL : string := "REGISTERED";
                        LPM_FILE : string := "UNUSED";
                        LPM_TYPE : string := "LPM_RAM_DP";
                        LPM_HINT : string := "UNUSED"
                );
                port (RDCLOCK : in std_logic := '0';
                        RDCLKEN : in std_logic := '1';
                        RDADDRESS : in std_logic_vector(LPM_WIDTHad-1 downto 0);
                        RDEN : in std_logic := '1';
                        DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
                        WRADDRESS : in std_logic_vector(LPM_WIDTHad-1 downto 0);
                        WREN : in std_logic;
                        WRCLOCK : in std_logic := '0';
                        WRCLKEN : in std_logic := '1';
                        Q : out std_logic_vector(LPM_WIDTH-1 downto 0)
                );
        END COMPONENT;
begin
        wren <= w_we_i and w_stb_i;
        rden <= not r_we_i and r_stb_i;
 
        w_ack_o <= '1'; -- 0-wait-state for writes
        r_ack_o <= '1'; -- 0-wait-state for reads
        sync_gen: if (not async_read) generate
                mem_core: lpm_ram_dp
                        GENERIC MAP (
                                lpm_width             => dat_width,
                                lpm_widthad           => adr_width,
                                lpm_indata            => "REGISTERED",
                                lpm_wraddress_control => "REGISTERED",
                                lpm_rdaddress_control => "REGISTERED",
                                lpm_outdata           => "UNREGISTERED",
                                lpm_hint              => "USE_EAB=ON"
                        )
                        PORT MAP (
                                rdclock   => r_clk_i,
                                wren      => wren,
                                wrclock   => w_clk_i,
                                q         => r_dat_o,
                                rden      => rden,
                                data      => w_dat_i,
                                rdaddress => r_adr_i,
                                wraddress => w_adr_i
                        );
        end generate;
        async_gen: if (async_read) generate
                mem_core: lpm_ram_dp
                        GENERIC MAP (
                                lpm_width             => dat_width,
                                lpm_widthad           => adr_width,
                                lpm_indata            => "REGISTERED",
                                lpm_wraddress_control => "REGISTERED",
                                lpm_rdaddress_control => "UNREGISTERED",
                                lpm_outdata           => "UNREGISTERED",
                                lpm_hint              => "USE_EAB=ON"
                        )
                        PORT MAP (
                                rdclock   => r_clk_i,
                                wren      => wren,
                                wrclock   => w_clk_i,
                                q         => r_dat_o,
                                rden      => rden,
                                data      => w_dat_i,
                                rdaddress => r_adr_i,
                                wraddress => w_adr_i
                        );
        end generate;
end altera;
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
library wb_tk;
use wb_tk.technology.all;
 
architecture altera of fifo is
        -- One additional bit is added to detect over and under-flow
        signal w_adr : std_logic_vector(adr_width downto 0);  -- internal write address
        signal r_adr : std_logic_vector(adr_width downto 0);  -- internal read address
begin
        read_proc : process (r_clk_i, reset)
        begin
                if reset = '1' then
                        r_adr     <= (others => '0');
                elsif r_clk_i'event and r_clk_i = '1' then
                        if (r_stb_i = '1' and r_we_i = '0') then
                                r_adr <= r_adr+"1";
                        end if;
                end if;
        end process read_proc;
 
        write_proc : process (w_clk_i, reset)
        begin
                if reset = '1' then
                        w_adr     <= (others => '0');
                elsif w_clk_i'event and w_clk_i = '1' then
                        if (w_stb_i = '1' and w_we_i = '1') then
                                w_adr <= w_adr+"1";
                        end if;
                end if;
        end process write_proc;
 
        empty_o <= '1' when r_adr = w_adr else '0';
        full_o  <= '1' when (w_adr(adr_width-1 downto 0) = r_adr(adr_width-1 downto 0)) and (w_adr(adr_width) /= r_adr(adr_width)) else '0';
        used_o <= w_adr - r_adr;
 
        mem_core: dpmem
        generic map (default_out,default_content,adr_width,dat_width,async_read)
        port map (
                -- signals for the read port
                r_clk_i            => r_clk_i,
                r_stb_i            => r_stb_i,
                r_we_i             => r_we_i,
                r_adr_i            => r_adr(adr_width-1 downto 0),
                r_dat_o            => r_dat_o,
                r_ack_o            => r_ack_o,
                -- signals for the write port
                w_clk_i            => w_clk_i,
                w_stb_i            => w_stb_i,
                w_we_i             => w_we_i,
                w_adr_i            => w_adr(adr_width-1 downto 0),
                w_dat_i            => w_dat_i,
                w_ack_o            => w_ack_o
        );
end altera;
 
library ieee;
use ieee.std_logic_1164.all;
library wb_tk;
use wb_tk.technology.all;
 
architecture altera of spmem is
        signal r_ack: std_logic;
        signal w_ack: std_logic;
begin
        mem_core: dpmem generic map (default_out,default_content,adr_width,dat_width,async_read)
                port map(
                        -- Signals for the read port
                        clk_i,
                        stb_i,
                        we_i,
                        adr_i,
                        dat_o,
                        r_ack,
                        -- Signals for the write port
                        clk_i,
                        stb_i,
                        we_i,
                        adr_i,
                        dat_i,
                        w_ack
                );
        ack_o <= '1';
end altera;

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[/] [wb_tk/] [trunk/] [technology_altera.vhd] - Blame information for rev 7

Line No.	Rev	Author	Line
1	6	tantos	`--`
2			`-- Technology mapping library. ALTERA edition.`
3			`--`
4			`-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31`
5			`-- This code is distributed under the terms and conditions of the GNU General Public Lince.`
6			`--`
7
8			`library IEEE;`
9			`use IEEE.std_logic_1164.all;`
10			`use IEEE.STD_LOGIC_UNSIGNED.all;`
11			`library exemplar;`
12			`--use exemplar.exemplar_1164.all;`
13			`library synopsys;`
14			`--use synopsys.std_logic_arith.all;`
15
16			`package body technology is`
17			`function to_std_logic_vector(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is`
18			`begin`
19			`return std_logic_arith.CONV_STD_LOGIC_VECTOR(arg,size);`
20			`end;`
21
22			`function to_integer(arg:std_logic_vector) return integer is`
23			`begin`
24			`return CONV_INTEGER(arg);`
25			`end;`
26
27			`-- function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is`
28			`-- begin`
29			`-- return exemplar_1164."+"(op_l, op_r);`
30			`-- end;`
31			`--`
32			`-- function "-"(op_l, op_r: std_logic_vector) return std_logic_vector is`
33			`-- begin`
34			`-- return exemplar_1164."-"(op_l, op_r);`
35			`-- end;`
36			`--`
37			`-- function add_one(inp : std_logic_vector) return std_logic_vector is`
38			`-- variable one: std_logic_vector(inp'RANGE) := (others => '0');`
39			`-- begin`
40			`-- one(0) := '1';`
41			`-- return exemplar_1164."+"(inp,one);`
42			`-- end;`
43			`--`
44			`-- function sub_one(inp : std_logic_vector) return std_logic_vector is`
45			`-- variable minus_one: std_logic_vector(inp'RANGE) := (others => '1');`
46			`-- begin`
47			`-- return exemplar_1164."+"(inp,minus_one);`
48			`-- end;`
49
50			`function is_zero(inp : std_logic_vector) return boolean is`
51			`variable zero: std_logic_vector(inp'RANGE) := (others => '0');`
52			`begin`
53			`return (inp = zero);`
54			`end;`
55
56			`function sl(l: std_logic_vector; r: integer) return std_logic_vector is`
57			`begin`
58			`return exemplar_1164.sl(l,r);`
59			`end;`
60
61			`function sr(l: std_logic_vector; r: integer) return std_logic_vector is`
62			`begin`
63			`return sl(l,-r);`
64			`end function;`
65
66			`function max2(a : integer; b: integer) return integer is`
67			`begin`
68			`if (a > b) then return a; end if;`
69			`return b;`
70			`end;`
71
72			`function min2(a : integer; b: integer) return integer is`
73			`begin`
74			`if (a < b) then return a; end if;`
75			`return b;`
76			`end;`
77
78			`function log2(inp : integer) return integer is`
79			`begin`
80			`if (inp < 1) then return 0; end if;`
81			`if (inp < 2) then return 0; end if;`
82			`if (inp < 4) then return 1; end if;`
83			`if (inp < 8) then return 2; end if;`
84			`if (inp < 16) then return 3; end if;`
85			`if (inp < 32) then return 4; end if;`
86			`if (inp < 64) then return 5; end if;`
87			`if (inp < 128) then return 6; end if;`
88			`if (inp < 256) then return 7; end if;`
89			`if (inp < 512) then return 8; end if;`
90			`if (inp < 1024) then return 9; end if;`
91			`if (inp < 2048) then return 10; end if;`
92			`if (inp < 4096) then return 11; end if;`
93			`if (inp < 8192) then return 12; end if;`
94			`if (inp < 16384) then return 13; end if;`
95			`if (inp < 32768) then return 14; end if;`
96			`if (inp < 65536) then return 15; end if;`
97			`return 16;`
98			`end;`
99
100			`function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer is`
101			`begin`
102			`if (in_bus = out_bus) then return 0; end if;`
103			`if (in_bus < out_bus) then return -log2(out_bus/in_bus); end if;`
104			`if (in_bus > out_bus) then return log2(in_bus/out_bus); end if;`
105			`end;`
106
107			`function size2bits(inp : integer) return integer is`
108			`begin`
109			`if (inp <= 1) then return 1; end if;`
110			`if (inp <= 2) then return 1; end if;`
111			`if (inp <= 4) then return 2; end if;`
112			`if (inp <= 8) then return 3; end if;`
113			`if (inp <= 16) then return 4; end if;`
114			`if (inp <= 32) then return 5; end if;`
115			`if (inp <= 64) then return 6; end if;`
116			`if (inp <= 128) then return 7; end if;`
117			`if (inp <= 256) then return 8; end if;`
118			`if (inp <= 512) then return 9; end if;`
119			`if (inp <= 1024) then return 10; end if;`
120			`if (inp <= 2048) then return 11; end if;`
121			`if (inp <= 4096) then return 12; end if;`
122			`if (inp <= 8192) then return 13; end if;`
123			`if (inp <= 16384) then return 14; end if;`
124			`if (inp <= 32768) then return 15; end if;`
125			`if (inp <= 65536) then return 16; end if;`
126			`return 17;`
127			`end;`
128
129			`function equ(a : std_logic_vector; b : integer) return boolean is`
130			`variable b_s : std_logic_vector(a'RANGE);`
131			`begin`
132			`b_s := to_std_logic_vector(b,a'HIGH+1);`
133			`return (a = b_s);`
134			`end;`
135
136			`end package body technology;`
137
138			`library IEEE;`
139			`use IEEE.std_logic_1164.all;`
140
141			`library altera;`
142			`use altera.maxplus2.all;`
143			`library alt_vtl;`
144			`use alt_vtl.all;`
145
146			`architecture altera of d_ff is`
147			`signal clrn,prn: std_logic;`
148			`begin`
149			`clrn <= not clr;`
150			`prn <= not pre;`
151			`ff: dffe port map (`
152			`D => d,`
153			`CLK => clk,`
154			`ENA => ena,`
155			`CLRN => clrn,`
156			`PRN => prn,`
157			`Q => q`
158			`);`
159			`end altera;`
160
161			`library ieee;`
162			`use ieee.std_logic_1164.all;`
163			`library wb_tk;`
164			`use wb_tk.technology.all;`
165			`library lpm;`
166			`use lpm.all;`
167
168			`-- GENERIC usage`
169			`-------------------`
170			`-- default_out : Not used in altera implementation`
171			`-- default_content : Not used in altera implementation`
172			`-- adr_width : Correctly used`
173			`-- dat_width : Correctly used`
174			`-- async_read : Correctly used`
175			`architecture altera of dpmem is`
176			`signal wren, rden: std_logic;`
177
178			`COMPONENT lpm_ram_dp`
179			`generic (LPM_WIDTH : positive;`
180			`LPM_WIDTHAD : positive;`
181			`LPM_NUMWORDS : natural := 0;`
182			`LPM_INDATA : string := "REGISTERED";`
183			`LPM_OUTDATA : string := "REGISTERED";`
184			`LPM_RDADDRESS_CONTROL : string := "REGISTERED";`
185			`LPM_WRADDRESS_CONTROL : string := "REGISTERED";`
186			`LPM_FILE : string := "UNUSED";`
187			`LPM_TYPE : string := "LPM_RAM_DP";`
188			`LPM_HINT : string := "UNUSED"`
189			`);`
190			`port (RDCLOCK : in std_logic := '0';`
191			`RDCLKEN : in std_logic := '1';`
192			`RDADDRESS : in std_logic_vector(LPM_WIDTHad-1 downto 0);`
193			`RDEN : in std_logic := '1';`
194			`DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);`
195			`WRADDRESS : in std_logic_vector(LPM_WIDTHad-1 downto 0);`
196			`WREN : in std_logic;`
197			`WRCLOCK : in std_logic := '0';`
198			`WRCLKEN : in std_logic := '1';`
199			`Q : out std_logic_vector(LPM_WIDTH-1 downto 0)`
200			`);`
201			`END COMPONENT;`
202			`begin`
203			`wren <= w_we_i and w_stb_i;`
204			`rden <= not r_we_i and r_stb_i;`
205
206			`w_ack_o <= '1'; -- 0-wait-state for writes`
207			`r_ack_o <= '1'; -- 0-wait-state for reads`
208			`sync_gen: if (not async_read) generate`
209			`mem_core: lpm_ram_dp`
210			`GENERIC MAP (`
211			`lpm_width => dat_width,`
212			`lpm_widthad => adr_width,`
213			`lpm_indata => "REGISTERED",`
214			`lpm_wraddress_control => "REGISTERED",`
215			`lpm_rdaddress_control => "REGISTERED",`
216			`lpm_outdata => "UNREGISTERED",`
217			`lpm_hint => "USE_EAB=ON"`
218			`)`
219			`PORT MAP (`
220			`rdclock => r_clk_i,`
221			`wren => wren,`
222			`wrclock => w_clk_i,`
223			`q => r_dat_o,`
224			`rden => rden,`
225			`data => w_dat_i,`
226			`rdaddress => r_adr_i,`
227			`wraddress => w_adr_i`
228			`);`
229			`end generate;`
230			`async_gen: if (async_read) generate`
231			`mem_core: lpm_ram_dp`
232			`GENERIC MAP (`
233			`lpm_width => dat_width,`
234			`lpm_widthad => adr_width,`
235			`lpm_indata => "REGISTERED",`
236			`lpm_wraddress_control => "REGISTERED",`
237			`lpm_rdaddress_control => "UNREGISTERED",`
238			`lpm_outdata => "UNREGISTERED",`
239			`lpm_hint => "USE_EAB=ON"`
240			`)`
241			`PORT MAP (`
242			`rdclock => r_clk_i,`
243			`wren => wren,`
244			`wrclock => w_clk_i,`
245			`q => r_dat_o,`
246			`rden => rden,`
247			`data => w_dat_i,`
248			`rdaddress => r_adr_i,`
249			`wraddress => w_adr_i`
250			`);`
251			`end generate;`
252			`end altera;`
253
254			`LIBRARY ieee;`
255			`USE ieee.std_logic_1164.ALL;`
256			`use IEEE.STD_LOGIC_UNSIGNED.all;`
257			`library wb_tk;`
258			`use wb_tk.technology.all;`
259
260			`architecture altera of fifo is`
261			`-- One additional bit is added to detect over and under-flow`
262			`signal w_adr : std_logic_vector(adr_width downto 0); -- internal write address`
263			`signal r_adr : std_logic_vector(adr_width downto 0); -- internal read address`
264			`begin`
265			`read_proc : process (r_clk_i, reset)`
266			`begin`
267			`if reset = '1' then`
268			`r_adr <= (others => '0');`
269			`elsif r_clk_i'event and r_clk_i = '1' then`
270			`if (r_stb_i = '1' and r_we_i = '0') then`
271			`r_adr <= r_adr+"1";`
272			`end if;`
273			`end if;`
274			`end process read_proc;`
275
276			`write_proc : process (w_clk_i, reset)`
277			`begin`
278			`if reset = '1' then`
279			`w_adr <= (others => '0');`
280			`elsif w_clk_i'event and w_clk_i = '1' then`
281			`if (w_stb_i = '1' and w_we_i = '1') then`
282			`w_adr <= w_adr+"1";`
283			`end if;`
284			`end if;`
285			`end process write_proc;`
286
287			`empty_o <= '1' when r_adr = w_adr else '0';`
288			`full_o <= '1' when (w_adr(adr_width-1 downto 0) = r_adr(adr_width-1 downto 0)) and (w_adr(adr_width) /= r_adr(adr_width)) else '0';`
289			`used_o <= w_adr - r_adr;`
290
291			`mem_core: dpmem`
292			`generic map (default_out,default_content,adr_width,dat_width,async_read)`
293			`port map (`
294			`-- signals for the read port`
295			`r_clk_i => r_clk_i,`
296			`r_stb_i => r_stb_i,`
297			`r_we_i => r_we_i,`
298			`r_adr_i => r_adr(adr_width-1 downto 0),`
299			`r_dat_o => r_dat_o,`
300			`r_ack_o => r_ack_o,`
301			`-- signals for the write port`
302			`w_clk_i => w_clk_i,`
303			`w_stb_i => w_stb_i,`
304			`w_we_i => w_we_i,`
305			`w_adr_i => w_adr(adr_width-1 downto 0),`
306			`w_dat_i => w_dat_i,`
307			`w_ack_o => w_ack_o`
308			`);`
309			`end altera;`
310
311			`library ieee;`
312			`use ieee.std_logic_1164.all;`
313			`library wb_tk;`
314			`use wb_tk.technology.all;`
315
316			`architecture altera of spmem is`
317			`signal r_ack: std_logic;`
318			`signal w_ack: std_logic;`
319			`begin`
320			`mem_core: dpmem generic map (default_out,default_content,adr_width,dat_width,async_read)`
321			`port map(`
322			`-- Signals for the read port`
323			`clk_i,`
324			`stb_i,`
325			`we_i,`
326			`adr_i,`
327			`dat_o,`
328			`r_ack,`
329			`-- Signals for the write port`
330			`clk_i,`
331			`stb_i,`
332			`we_i,`
333			`adr_i,`
334			`dat_i,`
335			`w_ack`
336			`);`
337			`ack_o <= '1';`
338			`end altera;`