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--
--  Technology mapping library. Behavioral edition.
--  Contains technology primitive implementations in a behavioral,
--  thus not 100% synthetizable form. Use this library to functional verification
--  and as a specification of thecnology primitives when porting to a particular
--  technology.
--
--  (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
--  This code is distributed under the terms and conditions of the GNU General Public Lince.
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
package body technology is
        function to_std_logic_vector(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
                variable RetVal: std_logic_vector(size-1 downto 0) := (others => '0');
                variable L_Arg: integer;
        begin
                L_Arg := ARG;
                if (L_Arg < 0) then L_Arg := -L_Arg; end if;
                for i in 0 to SIZE-1 loop
                        if (L_Arg mod 2) = 1 then
                                RetVal(i) := '1';
                        end if;
                        L_Arg := L_Arg/2;
                end loop;
                -- Compute two's complement if arg was negative
                if (ARG < 0) then
                        RetVal := not RetVal;
                        RetVal := RetVal+"1";
                end if;
                return RetVal;
        end;
        function to_integer(arg:std_logic_vector) return integer is
        begin
                return CONV_INTEGER(arg);
        end;
 
 
--      function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is
--      begin
--              return to_std_logic_vector(to_integer(op_l)+to_integer(op_r),max2(op_l'length, op_r'length));
--      end;
--
--      function "-"(op_l, op_r: std_logic_vector) return std_logic_vector is
--      begin
--              return to_std_logic_vector(to_integer(op_l)-to_integer(op_r),max2(op_l'length, op_r'length));
--      end;
--
--      function add_one(inp : std_logic_vector) return std_logic_vector is
--      begin
--              return to_std_logic_vector(to_integer(inp)+1,inp'length);
--      end;
--
--      function sub_one(inp : std_logic_vector) return std_logic_vector is
--      begin
--              return to_std_logic_vector(to_integer(inp)-1,inp'length);
--      end;
 
        function is_zero(inp : std_logic_vector) return boolean is
                variable zero: std_logic_vector(inp'RANGE) := (others => '0');
        begin
--              return std_logic_unsigned."="(inp,zero);
                return inp = zero;
        end;
 
        function sl(l: std_logic_vector; r: integer) return std_logic_vector is
                variable RetVal : std_logic_vector (l'length-1 downto 0) ;
                variable LL: std_logic_vector(l'length-1 downto 0) := l;
        begin
                RetVal := (others => '0');
                if (ABS(r) < l'length) then
                        if (r >= 0) then
                                RetVal(l'length-1 downto r) :=  ll(l'length-1-r downto 0);
                        else -- (r < 0)
                                RetVal(l'length-1+r downto 0) := ll(l'length-1 downto -r);
                        end if ;
                end if;
                return RetVal ;
        end sl ;
 
        function sr(l: std_logic_vector; r: integer) return std_logic_vector is
        begin
                return sl(l,-r);
        end sr;
 
        function max2(a : integer; b: integer) return integer is
        begin
                if (a > b) then return a; end if;
                return b;
        end;
 
        function min2(a : integer; b: integer) return integer is
        begin
                if (a < b) then return a; end if;
                return b;
        end;
 
        function log2(inp : integer) return integer is
        begin
                if (inp < 1) then return 0; end if;
                if (inp < 2) then return 0; end if;
                if (inp < 4) then return 1; end if;
                if (inp < 8) then return 2; end if;
                if (inp < 16) then return 3; end if;
                if (inp < 32) then return 4; end if;
                if (inp < 64) then return 5; end if;
                if (inp < 128) then return 6; end if;
                if (inp < 256) then return 7; end if;
                if (inp < 512) then return 8; end if;
                if (inp < 1024) then return 9; end if;
                if (inp < 2048) then return 10; end if;
                if (inp < 4096) then return 11; end if;
                if (inp < 8192) then return 12; end if;
                if (inp < 16384) then return 13; end if;
                if (inp < 32768) then return 14; end if;
                if (inp < 65536) then return 15; end if;
                return 16;
        end;
 
        function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer is
        begin
                if (in_bus = out_bus) then return 0; end if;
                if (in_bus < out_bus) then return -log2(out_bus/in_bus); end if;
                if (in_bus > out_bus) then return log2(in_bus/out_bus); end if;
        end;
 
        function size2bits(inp : integer) return integer is
        begin
                if (inp <= 1) then return 1; end if;
                if (inp <= 2) then return 1; end if;
                if (inp <= 4) then return 2; end if;
                if (inp <= 8) then return 3; end if;
                if (inp <= 16) then return 4; end if;
                if (inp <= 32) then return 5; end if;
                if (inp <= 64) then return 6; end if;
                if (inp <= 128) then return 7; end if;
                if (inp <= 256) then return 8; end if;
                if (inp <= 512) then return 9; end if;
                if (inp <= 1024) then return 10; end if;
                if (inp <= 2048) then return 11; end if;
                if (inp <= 4096) then return 12; end if;
                if (inp <= 8192) then return 13; end if;
                if (inp <= 16384) then return 14; end if;
                if (inp <= 32768) then return 15; end if;
                if (inp <= 65536) then return 16; end if;
                return 17;
        end;
 
        function equ(a : std_logic_vector; b : integer) return boolean is
                variable b_s : std_logic_vector(a'RANGE);
        begin
                b_s := to_std_logic_vector(b,a'HIGH+1);
                return a = b_s;
        end;
 
end technology;
 
library IEEE;
use IEEE.std_logic_1164.all;
 
architecture behavioral of d_ff is
        signal l_q: STD_LOGIC := 'X';
begin
        d_ff: process
                variable clrpre: std_logic_vector(1 downto 0);
        begin
                wait until clk'EVENT or clr'EVENT or pre'EVENT;
                clrpre := clr & pre;
                case clrpre is
                        when "10" =>
                                l_q <= '0';
                        when "01" =>
                                l_q <= '1';
                        when "11" =>
                                --assert true report "Set and preset cannot be active at the same time" severity error;
                                l_q <= 'X';
                        when "00" =>
                                if (clk'EVENT) then
                                        if (clk = '1') then
                                                if (ena = '1') then
                                                        l_q <= d;
                                                else
                                                        if (ena /= '0') then
                                                                l_q <= 'X';
                                                        end if;
                                                end if;
                                        end if;
                                end if;
                        when others =>
                                l_q <= 'X';
                end case;
        end process;
        q <= l_q;
 
end behavioral;
 
library ieee;
use ieee.std_logic_1164.all;
library wb_tk;
use wb_tk.technology.all;
 
architecture behavioral of dpmem is
        type data_array is array (integer range <>) of std_logic_vector(dat_width-1 downto 0);         -- Memory Type
        signal data : data_array(0 to (2** adr_width-1) ) := (others => (others => default_content));  -- Local data
        signal r_clk: std_logic;
        signal l_r_ack: std_logic := '0';
begin
        async_clk: if (async_read) generate
                r_dat_o <= data(to_integer(r_adr_i)) when (r_stb_i = '1' and r_we_i = '0') else (others => default_out);
                r_ack_o <= '1'; -- async read is 0 wait-state
        end generate;
        sync_clk: if (not async_read) generate
                ReProc : process (r_clk_i)
                begin
                        if r_clk_i'event and r_clk_i = '1' then
                                if r_stb_i = '1' and r_we_i = '0' then
                                        r_dat_o <= data(to_integer(r_adr_i));
                                        l_r_ack <= not l_r_ack;
                                else
                                        r_dat_o <= (others => default_out);
                                        l_r_ack <= '0';
                                end if;
                        end if;
                end process ReProc;
                r_ack_o <= l_r_ack;
        end generate;
 
        w_ack_o <= '1'; -- write is allways 0 wait-state
        WrProc : process (w_clk_i)
        begin
                if w_clk_i'event and w_clk_i = '1' then
                        if w_stb_i = '1' and w_we_i = '1' then
                                data(to_integer(w_adr_i)) <= w_dat_i;
                        end if;
                end if;
        end process WrProc;
end behavioral;
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
library wb_tk;
use wb_tk.technology.all;
 
architecture behavioral of fifo is
        -- One additional bit is added to detect over and under-flow
        signal w_adr : std_logic_vector(adr_width downto 0);  -- internal write address
        signal r_adr : std_logic_vector(adr_width downto 0);  -- internal read address
        signal w_ack, r_ack: std_logic;
begin
        read_proc : process (r_clk_i, reset)
        begin
                if reset = '1' then
                        r_adr     <= (others => '0');
                elsif r_clk_i'event and r_clk_i = '1' then
                        if (r_stb_i = '1' and r_we_i = '0' and r_ack = '1') then
                                r_adr <= r_adr+"1";
                        end if;
                end if;
        end process read_proc;
 
        write_proc : process (w_clk_i, reset)
        begin
                if reset = '1' then
                        w_adr     <= (others => '0');
                elsif w_clk_i'event and w_clk_i = '1' then
                        if (w_stb_i = '1' and w_we_i = '1' and w_ack = '1') then
                                w_adr <= w_adr+"1";
                        end if;
                end if;
        end process write_proc;
 
        empty_o <= '1' when r_adr = w_adr else '0';
        full_o  <= '1' when (w_adr(adr_width-1 downto 0) = r_adr(adr_width-1 downto 0)) and (w_adr(adr_width) /= r_adr(adr_width)) else '0';
        used_o <= w_adr - r_adr;
 
        mem_core: dpmem
        generic map (default_out,default_content,adr_width,dat_width,async_read)
        port map (
                -- signals for the read port
                r_clk_i            => r_clk_i,
                r_stb_i            => r_stb_i,
                r_we_i             => r_we_i,
                r_adr_i            => r_adr(adr_width-1 downto 0),
                r_dat_o            => r_dat_o,
                r_ack_o            => r_ack,
                -- signals for the write port
                w_clk_i            => w_clk_i,
                w_stb_i            => w_stb_i,
                w_we_i             => w_we_i,
                w_adr_i            => w_adr(adr_width-1 downto 0),
                w_dat_i            => w_dat_i,
                w_ack_o            => w_ack
        );
end behavioral;
 
library ieee;
use ieee.std_logic_1164.all;
library wb_tk;
use wb_tk.technology.all;
 
architecture behavioral of spmem is
        signal w_ack, r_ack: std_logic;
begin
        mem_core: dpmem generic map (default_out,default_content,adr_width,dat_width,async_read)
                port map(
                        -- Signals for the read port
                        clk_i,
                        stb_i,
                        we_i,
                        adr_i,
                        dat_o,
                        r_ack,
                        -- Signals for the write port
                        clk_i,
                        stb_i,
                        we_i,
                        adr_i,
                        dat_i,
                        w_ack
        );
        ack_o <= ('0' and not stb_i) or (r_ack and (stb_i and not we_i)) or (w_ack and (stb_i and we_i));
end behavioral;

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[/] [wb_tk/] [trunk/] [technology_behav.vhd] - Blame information for rev 7

Line No.	Rev	Author	Line
1	6	tantos	`--`
2			`-- Technology mapping library. Behavioral edition.`
3			`-- Contains technology primitive implementations in a behavioral,`
4			`-- thus not 100% synthetizable form. Use this library to functional verification`
5			`-- and as a specification of thecnology primitives when porting to a particular`
6			`-- technology.`
7			`--`
8			`-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31`
9			`-- This code is distributed under the terms and conditions of the GNU General Public Lince.`
10			`--`
11
12			`library IEEE;`
13			`use IEEE.std_logic_1164.all;`
14			`use IEEE.STD_LOGIC_UNSIGNED.all;`
15
16			`package body technology is`
17			`function to_std_logic_vector(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is`
18			`variable RetVal: std_logic_vector(size-1 downto 0) := (others => '0');`
19			`variable L_Arg: integer;`
20			`begin`
21			`L_Arg := ARG;`
22			`if (L_Arg < 0) then L_Arg := -L_Arg; end if;`
23			`for i in 0 to SIZE-1 loop`
24			`if (L_Arg mod 2) = 1 then`
25			`RetVal(i) := '1';`
26			`end if;`
27			`L_Arg := L_Arg/2;`
28			`end loop;`
29			`-- Compute two's complement if arg was negative`
30			`if (ARG < 0) then`
31			`RetVal := not RetVal;`
32			`RetVal := RetVal+"1";`
33			`end if;`
34			`return RetVal;`
35			`end;`
36			`function to_integer(arg:std_logic_vector) return integer is`
37			`begin`
38			`return CONV_INTEGER(arg);`
39			`end;`
40
41
42			`-- function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is`
43			`-- begin`
44			`-- return to_std_logic_vector(to_integer(op_l)+to_integer(op_r),max2(op_l'length, op_r'length));`
45			`-- end;`
46			`--`
47			`-- function "-"(op_l, op_r: std_logic_vector) return std_logic_vector is`
48			`-- begin`
49			`-- return to_std_logic_vector(to_integer(op_l)-to_integer(op_r),max2(op_l'length, op_r'length));`
50			`-- end;`
51			`--`
52			`-- function add_one(inp : std_logic_vector) return std_logic_vector is`
53			`-- begin`
54			`-- return to_std_logic_vector(to_integer(inp)+1,inp'length);`
55			`-- end;`
56			`--`
57			`-- function sub_one(inp : std_logic_vector) return std_logic_vector is`
58			`-- begin`
59			`-- return to_std_logic_vector(to_integer(inp)-1,inp'length);`
60			`-- end;`
61
62			`function is_zero(inp : std_logic_vector) return boolean is`
63			`variable zero: std_logic_vector(inp'RANGE) := (others => '0');`
64			`begin`
65			`-- return std_logic_unsigned."="(inp,zero);`
66			`return inp = zero;`
67			`end;`
68
69			`function sl(l: std_logic_vector; r: integer) return std_logic_vector is`
70			`variable RetVal : std_logic_vector (l'length-1 downto 0) ;`
71			`variable LL: std_logic_vector(l'length-1 downto 0) := l;`
72			`begin`
73			`RetVal := (others => '0');`
74			`if (ABS(r) < l'length) then`
75			`if (r >= 0) then`
76			`RetVal(l'length-1 downto r) := ll(l'length-1-r downto 0);`
77			`else -- (r < 0)`
78			`RetVal(l'length-1+r downto 0) := ll(l'length-1 downto -r);`
79			`end if ;`
80			`end if;`
81			`return RetVal ;`
82			`end sl ;`
83
84			`function sr(l: std_logic_vector; r: integer) return std_logic_vector is`
85			`begin`
86			`return sl(l,-r);`
87			`end sr;`
88
89			`function max2(a : integer; b: integer) return integer is`
90			`begin`
91			`if (a > b) then return a; end if;`
92			`return b;`
93			`end;`
94
95			`function min2(a : integer; b: integer) return integer is`
96			`begin`
97			`if (a < b) then return a; end if;`
98			`return b;`
99			`end;`
100
101			`function log2(inp : integer) return integer is`
102			`begin`
103			`if (inp < 1) then return 0; end if;`
104			`if (inp < 2) then return 0; end if;`
105			`if (inp < 4) then return 1; end if;`
106			`if (inp < 8) then return 2; end if;`
107			`if (inp < 16) then return 3; end if;`
108			`if (inp < 32) then return 4; end if;`
109			`if (inp < 64) then return 5; end if;`
110			`if (inp < 128) then return 6; end if;`
111			`if (inp < 256) then return 7; end if;`
112			`if (inp < 512) then return 8; end if;`
113			`if (inp < 1024) then return 9; end if;`
114			`if (inp < 2048) then return 10; end if;`
115			`if (inp < 4096) then return 11; end if;`
116			`if (inp < 8192) then return 12; end if;`
117			`if (inp < 16384) then return 13; end if;`
118			`if (inp < 32768) then return 14; end if;`
119			`if (inp < 65536) then return 15; end if;`
120			`return 16;`
121			`end;`
122
123			`function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer is`
124			`begin`
125			`if (in_bus = out_bus) then return 0; end if;`
126			`if (in_bus < out_bus) then return -log2(out_bus/in_bus); end if;`
127			`if (in_bus > out_bus) then return log2(in_bus/out_bus); end if;`
128			`end;`
129
130			`function size2bits(inp : integer) return integer is`
131			`begin`
132			`if (inp <= 1) then return 1; end if;`
133			`if (inp <= 2) then return 1; end if;`
134			`if (inp <= 4) then return 2; end if;`
135			`if (inp <= 8) then return 3; end if;`
136			`if (inp <= 16) then return 4; end if;`
137			`if (inp <= 32) then return 5; end if;`
138			`if (inp <= 64) then return 6; end if;`
139			`if (inp <= 128) then return 7; end if;`
140			`if (inp <= 256) then return 8; end if;`
141			`if (inp <= 512) then return 9; end if;`
142			`if (inp <= 1024) then return 10; end if;`
143			`if (inp <= 2048) then return 11; end if;`
144			`if (inp <= 4096) then return 12; end if;`
145			`if (inp <= 8192) then return 13; end if;`
146			`if (inp <= 16384) then return 14; end if;`
147			`if (inp <= 32768) then return 15; end if;`
148			`if (inp <= 65536) then return 16; end if;`
149			`return 17;`
150			`end;`
151
152			`function equ(a : std_logic_vector; b : integer) return boolean is`
153			`variable b_s : std_logic_vector(a'RANGE);`
154			`begin`
155			`b_s := to_std_logic_vector(b,a'HIGH+1);`
156			`return a = b_s;`
157			`end;`
158
159			`end technology;`
160
161			`library IEEE;`
162			`use IEEE.std_logic_1164.all;`
163
164			`architecture behavioral of d_ff is`
165			`signal l_q: STD_LOGIC := 'X';`
166			`begin`
167			`d_ff: process`
168			`variable clrpre: std_logic_vector(1 downto 0);`
169			`begin`
170			`wait until clk'EVENT or clr'EVENT or pre'EVENT;`
171			`clrpre := clr & pre;`
172			`case clrpre is`
173			`when "10" =>`
174			`l_q <= '0';`
175			`when "01" =>`
176			`l_q <= '1';`
177			`when "11" =>`
178			`--assert true report "Set and preset cannot be active at the same time" severity error;`
179			`l_q <= 'X';`
180			`when "00" =>`
181			`if (clk'EVENT) then`
182			`if (clk = '1') then`
183			`if (ena = '1') then`
184			`l_q <= d;`
185			`else`
186			`if (ena /= '0') then`
187			`l_q <= 'X';`
188			`end if;`
189			`end if;`
190			`end if;`
191			`end if;`
192			`when others =>`
193			`l_q <= 'X';`
194			`end case;`
195			`end process;`
196			`q <= l_q;`
197
198			`end behavioral;`
199
200			`library ieee;`
201			`use ieee.std_logic_1164.all;`
202			`library wb_tk;`
203			`use wb_tk.technology.all;`
204
205			`architecture behavioral of dpmem is`
206			`type data_array is array (integer range <>) of std_logic_vector(dat_width-1 downto 0); -- Memory Type`
207			`signal data : data_array(0 to (2** adr_width-1) ) := (others => (others => default_content)); -- Local data`
208			`signal r_clk: std_logic;`
209			`signal l_r_ack: std_logic := '0';`
210			`begin`
211			`async_clk: if (async_read) generate`
212			`r_dat_o <= data(to_integer(r_adr_i)) when (r_stb_i = '1' and r_we_i = '0') else (others => default_out);`
213			`r_ack_o <= '1'; -- async read is 0 wait-state`
214			`end generate;`
215			`sync_clk: if (not async_read) generate`
216			`ReProc : process (r_clk_i)`
217			`begin`
218			`if r_clk_i'event and r_clk_i = '1' then`
219			`if r_stb_i = '1' and r_we_i = '0' then`
220			`r_dat_o <= data(to_integer(r_adr_i));`
221			`l_r_ack <= not l_r_ack;`
222			`else`
223			`r_dat_o <= (others => default_out);`
224			`l_r_ack <= '0';`
225			`end if;`
226			`end if;`
227			`end process ReProc;`
228			`r_ack_o <= l_r_ack;`
229			`end generate;`
230
231			`w_ack_o <= '1'; -- write is allways 0 wait-state`
232			`WrProc : process (w_clk_i)`
233			`begin`
234			`if w_clk_i'event and w_clk_i = '1' then`
235			`if w_stb_i = '1' and w_we_i = '1' then`
236			`data(to_integer(w_adr_i)) <= w_dat_i;`
237			`end if;`
238			`end if;`
239			`end process WrProc;`
240			`end behavioral;`
241
242			`LIBRARY ieee;`
243			`USE ieee.std_logic_1164.ALL;`
244			`use IEEE.STD_LOGIC_UNSIGNED.all;`
245			`library wb_tk;`
246			`use wb_tk.technology.all;`
247
248			`architecture behavioral of fifo is`
249			`-- One additional bit is added to detect over and under-flow`
250			`signal w_adr : std_logic_vector(adr_width downto 0); -- internal write address`
251			`signal r_adr : std_logic_vector(adr_width downto 0); -- internal read address`
252			`signal w_ack, r_ack: std_logic;`
253			`begin`
254			`read_proc : process (r_clk_i, reset)`
255			`begin`
256			`if reset = '1' then`
257			`r_adr <= (others => '0');`
258			`elsif r_clk_i'event and r_clk_i = '1' then`
259			`if (r_stb_i = '1' and r_we_i = '0' and r_ack = '1') then`
260			`r_adr <= r_adr+"1";`
261			`end if;`
262			`end if;`
263			`end process read_proc;`
264
265			`write_proc : process (w_clk_i, reset)`
266			`begin`
267			`if reset = '1' then`
268			`w_adr <= (others => '0');`
269			`elsif w_clk_i'event and w_clk_i = '1' then`
270			`if (w_stb_i = '1' and w_we_i = '1' and w_ack = '1') then`
271			`w_adr <= w_adr+"1";`
272			`end if;`
273			`end if;`
274			`end process write_proc;`
275
276			`empty_o <= '1' when r_adr = w_adr else '0';`
277			`full_o <= '1' when (w_adr(adr_width-1 downto 0) = r_adr(adr_width-1 downto 0)) and (w_adr(adr_width) /= r_adr(adr_width)) else '0';`
278			`used_o <= w_adr - r_adr;`
279
280			`mem_core: dpmem`
281			`generic map (default_out,default_content,adr_width,dat_width,async_read)`
282			`port map (`
283			`-- signals for the read port`
284			`r_clk_i => r_clk_i,`
285			`r_stb_i => r_stb_i,`
286			`r_we_i => r_we_i,`
287			`r_adr_i => r_adr(adr_width-1 downto 0),`
288			`r_dat_o => r_dat_o,`
289			`r_ack_o => r_ack,`
290			`-- signals for the write port`
291			`w_clk_i => w_clk_i,`
292			`w_stb_i => w_stb_i,`
293			`w_we_i => w_we_i,`
294			`w_adr_i => w_adr(adr_width-1 downto 0),`
295			`w_dat_i => w_dat_i,`
296			`w_ack_o => w_ack`
297			`);`
298			`end behavioral;`
299
300			`library ieee;`
301			`use ieee.std_logic_1164.all;`
302			`library wb_tk;`
303			`use wb_tk.technology.all;`
304
305			`architecture behavioral of spmem is`
306			`signal w_ack, r_ack: std_logic;`
307			`begin`
308			`mem_core: dpmem generic map (default_out,default_content,adr_width,dat_width,async_read)`
309			`port map(`
310			`-- Signals for the read port`
311			`clk_i,`
312			`stb_i,`
313			`we_i,`
314			`adr_i,`
315			`dat_o,`
316			`r_ack,`
317			`-- Signals for the write port`
318			`clk_i,`
319			`stb_i,`
320			`we_i,`
321			`adr_i,`
322			`dat_i,`
323			`w_ack`
324			`);`
325			`ack_o <= ('0' and not stb_i) or (r_ack and (stb_i and not we_i)) or (w_ack and (stb_i and we_i));`
326			`end behavioral;`