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[/] [wb_tk/] [trunk/] [wb_bus_resize.vhd] - Blame information for rev 7

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Line No. Rev Author Line
1 4 tantos 
--
2 
--  Wishbone bus toolkit.
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--
4 
--  (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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--  This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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-- ELEMENTS:
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--   wb_bus_resize: bus resizer.
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11 
-------------------------------------------------------------------------------
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--
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--  wb_bus_resize
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--
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-------------------------------------------------------------------------------
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17 
library IEEE;
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use IEEE.std_logic_1164.all;
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library wb_tk;
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use wb_tk.technology.all;
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22 
entity wb_bus_resize is
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        generic (
24 6 tantos 
                m_dat_width: positive := 32; -- master bus width
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                m_adr_width: positive := 19; -- master bus width
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                s_dat_width: positive := 16; -- slave bus width
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                s_adr_width: positive := 20; -- master bus width
28 4 tantos 
                little_endien: boolean := true -- if set to false, big endien
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        );
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        port (
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--              clk_i: in std_logic;
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--              rst_i: in std_logic := '0';
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                -- Master bus interface
35 6 tantos 
                m_adr_i: in std_logic_vector (m_adr_width-1 downto 0);
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                m_sel_i: in std_logic_vector ((m_dat_width/8)-1 downto 0) := (others => '1');
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                m_dat_i: in std_logic_vector (m_dat_width-1 downto 0);
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                m_dat_oi: in std_logic_vector (m_dat_width-1 downto 0) := (others => '-');
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                m_dat_o: out std_logic_vector (m_dat_width-1 downto 0);
40 4 tantos 
                m_cyc_i: in std_logic;
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                m_ack_o: out std_logic;
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                m_ack_oi: in std_logic := '-';
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                m_err_o: out std_logic;
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                m_err_oi: in std_logic := '-';
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                m_rty_o: out std_logic;
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                m_rty_oi: in std_logic := '-';
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                m_we_i: in std_logic;
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                m_stb_i: in std_logic;
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50 
                -- Slave bus interface
51 6 tantos 
                s_adr_o: out std_logic_vector (s_adr_width-1 downto 0);
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                s_sel_o: out std_logic_vector ((s_dat_width/8)-1 downto 0);
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                s_dat_i: in std_logic_vector (s_dat_width-1 downto 0);
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                s_dat_o: out std_logic_vector (s_dat_width-1 downto 0);
55 4 tantos 
                s_cyc_o: out std_logic;
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                s_ack_i: in std_logic;
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                s_err_i: in std_logic := '-';
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                s_rty_i: in std_logic := '-';
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                s_we_o: out std_logic;
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                s_stb_o: out std_logic
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        );
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end wb_bus_resize;
63 
 
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architecture wb_bus_resize of wb_bus_resize is
65 6 tantos 
        component wb_bus_upsize
66 4 tantos 
                generic (
67 6 tantos 
                        m_dat_width: positive := 8; -- master bus width
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                        m_adr_width: positive := 21; -- master bus width
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                        s_dat_width: positive := 16; -- slave bus width
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                        s_adr_width: positive := 20; -- master bus width
71 4 tantos 
                        little_endien: boolean := true -- if set to false, big endien
72 
                );
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                port (
74 
        --              clk_i: in std_logic;
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        --              rst_i: in std_logic := '0';
76 6 tantos 
 
77 4 tantos 
                        -- Master bus interface
78 6 tantos 
                        m_adr_i: in std_logic_vector (m_adr_width-1 downto 0);
79 
                        m_sel_i: in std_logic_vector ((m_dat_width/8)-1 downto 0) := (others => '1');
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                        m_dat_i: in std_logic_vector (m_dat_width-1 downto 0);
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                        m_dat_oi: in std_logic_vector (m_dat_width-1 downto 0) := (others => '-');
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                        m_dat_o: out std_logic_vector (m_dat_width-1 downto 0);
83 4 tantos 
                        m_cyc_i: in std_logic;
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                        m_ack_o: out std_logic;
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                        m_ack_oi: in std_logic := '-';
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                        m_err_o: out std_logic;
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                        m_err_oi: in std_logic := '-';
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                        m_rty_o: out std_logic;
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                        m_rty_oi: in std_logic := '-';
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                        m_we_i: in std_logic;
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                        m_stb_i: in std_logic;
92 6 tantos 
 
93 4 tantos 
                        -- Slave bus interface
94 6 tantos 
                        s_adr_o: out std_logic_vector (s_adr_width-1 downto 0);
95 
                        s_sel_o: out std_logic_vector ((s_dat_width/8)-1 downto 0);
96 
                        s_dat_i: in std_logic_vector (s_dat_width-1 downto 0);
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                        s_dat_o: out std_logic_vector (s_dat_width-1 downto 0);
98 4 tantos 
                        s_cyc_o: out std_logic;
99 
                        s_ack_i: in std_logic;
100 
                        s_err_i: in std_logic := '-';
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                        s_rty_i: in std_logic := '-';
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                        s_we_o: out std_logic;
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                        s_stb_o: out std_logic
104 
                );
105 
        end component;
106 
 
107 6 tantos 
        component wb_bus_dnsize
108 4 tantos 
                generic (
109 6 tantos 
                        m_dat_width: positive := 32; -- master bus width
110 
                        m_adr_width: positive := 20; -- master bus width
111 
                        s_dat_width: positive := 16; -- slave bus width
112 
                        s_adr_width: positive := 21; -- master bus width
113 4 tantos 
                        little_endien: boolean := true -- if set to false, big endien
114 
                );
115 
                port (
116 
        --              clk_i: in std_logic;
117 
        --              rst_i: in std_logic := '0';
118 6 tantos 
 
119 4 tantos 
                        -- Master bus interface
120 6 tantos 
                        m_adr_i: in std_logic_vector (m_adr_width-1 downto 0);
121 
                        m_sel_i: in std_logic_vector ((m_dat_width/8)-1 downto 0) := (others => '1');
122 
                        m_dat_i: in std_logic_vector (m_dat_width-1 downto 0);
123 
                        m_dat_oi: in std_logic_vector (m_dat_width-1 downto 0) := (others => '-');
124 
                        m_dat_o: out std_logic_vector (m_dat_width-1 downto 0);
125 4 tantos 
                        m_cyc_i: in std_logic;
126 
                        m_ack_o: out std_logic;
127 
                        m_ack_oi: in std_logic := '-';
128 
                        m_err_o: out std_logic;
129 
                        m_err_oi: in std_logic := '-';
130 
                        m_rty_o: out std_logic;
131 
                        m_rty_oi: in std_logic := '-';
132 
                        m_we_i: in std_logic;
133 
                        m_stb_i: in std_logic;
134 6 tantos 
 
135 4 tantos 
                        -- Slave bus interface
136 6 tantos 
                        s_adr_o: out std_logic_vector (s_adr_width-1 downto 0);
137 
                        s_sel_o: out std_logic_vector ((s_dat_width/8)-1 downto 0);
138 
                        s_dat_i: in std_logic_vector (s_dat_width-1 downto 0);
139 
                        s_dat_o: out std_logic_vector (s_dat_width-1 downto 0);
140 4 tantos 
                        s_cyc_o: out std_logic;
141 
                        s_ack_i: in std_logic;
142 
                        s_err_i: in std_logic := '-';
143 
                        s_rty_i: in std_logic := '-';
144 
                        s_we_o: out std_logic;
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                        s_stb_o: out std_logic
146 
                );
147 
        end component;
148 
begin
149 6 tantos 
        dn_sel: if (m_dat_width > s_dat_width) generate
150 4 tantos 
                dnsizer: wb_bus_dnsize
151 
                        generic map (
152 6 tantos 
                                m_dat_width => m_dat_width,
153 
                                m_adr_width => m_adr_width,
154 
                                s_dat_width => s_dat_width,
155 
                                s_adr_width => s_adr_width,
156 4 tantos 
                                little_endien => little_endien
157 
                        )
158 
                        port map
159 
                                (m_adr_i => m_adr_i,
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                                m_sel_i => m_sel_i,
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                                m_dat_i => m_dat_i,
162 
                                m_dat_oi => m_dat_oi,
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                                m_dat_o => m_dat_o,
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                                m_cyc_i => m_cyc_i,
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                                m_ack_o => m_ack_o,
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                                m_ack_oi => m_ack_oi,
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                                m_err_o => m_err_o,
168 
                                m_err_oi => m_err_oi,
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                                m_rty_o => m_rty_o,
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                                m_rty_oi => m_rty_oi,
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                                m_we_i => m_we_i,
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                                m_stb_i => m_stb_i,
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                                s_adr_o => s_adr_o,
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                                s_sel_o => s_sel_o,
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                                s_dat_i => s_dat_i,
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                                s_dat_o => s_dat_o,
177 
                                s_cyc_o => s_cyc_o,
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                                s_ack_i => s_ack_i,
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                                s_err_i => s_err_i,
180 
                                s_rty_i => s_rty_i,
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                                s_we_o => s_we_o,
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                                s_stb_o => s_stb_o
183 
                        );
184 
        end generate;
185 6 tantos 
        up_sel: if (m_dat_width < s_dat_width) generate
186 4 tantos 
                upsizer: wb_bus_upsize
187 
                        generic map (
188 6 tantos 
                                m_dat_width => m_dat_width,
189 
                                m_adr_width => m_adr_width,
190 
                                s_dat_width => s_dat_width,
191 
                                s_adr_width => s_adr_width,
192 4 tantos 
                                little_endien => little_endien
193 
                        )
194 
                        port map
195 
                                (m_adr_i => m_adr_i,
196 
                                m_sel_i => m_sel_i,
197 
                                m_dat_i => m_dat_i,
198 
                                m_dat_oi => m_dat_oi,
199 
                                m_dat_o => m_dat_o,
200 
                                m_cyc_i => m_cyc_i,
201 
                                m_ack_o => m_ack_o,
202 
                                m_ack_oi => m_ack_oi,
203 
                                m_err_o => m_err_o,
204 
                                m_err_oi => m_err_oi,
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                                m_rty_o => m_rty_o,
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                                m_rty_oi => m_rty_oi,
207 
                                m_we_i => m_we_i,
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                                m_stb_i => m_stb_i,
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                                s_adr_o => s_adr_o,
210 
                                s_sel_o => s_sel_o,
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                                s_dat_i => s_dat_i,
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                                s_dat_o => s_dat_o,
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                                s_cyc_o => s_cyc_o,
214 
                                s_ack_i => s_ack_i,
215 
                                s_err_i => s_err_i,
216 
                                s_rty_i => s_rty_i,
217 
                                s_we_o => s_we_o,
218 
                                s_stb_o => s_stb_o
219 
                        );
220 
        end generate;
221 6 tantos 
        eq_sel: if (m_dat_width = s_dat_width) generate
222 4 tantos 
                dat_o_for: for i in m_dat_o'RANGE generate
223 
                        dat_o_gen: m_dat_o(i) <= (s_dat_i(i) and m_stb_i and not m_we_i) or (m_dat_oi(i) and not (m_stb_i and not m_we_i));
224 
                end generate;
225 
                m_ack_o <= (s_ack_i and m_stb_i and not m_we_i) or (m_ack_oi and not (m_stb_i and not m_we_i));
226 
                m_err_o <= (s_err_i and m_stb_i and not m_we_i) or (m_err_oi and not (m_stb_i and not m_we_i));
227 
                m_rty_o <= (s_rty_i and m_stb_i and not m_we_i) or (m_rty_oi and not (m_stb_i and not m_we_i));
228 
                s_adr_o <= m_adr_i;
229 
                s_sel_o <= m_sel_i;
230 
                s_dat_o <= m_dat_i;
231 
                s_cyc_o <= m_cyc_i;
232 
                s_we_o <= m_we_i;
233 
                s_stb_o <= m_stb_i;
234 
        end generate;
235 
end wb_bus_resize;
236 
 

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