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--
--  Wishbone bus tester utilities.
--
--  (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/04/17
--  This code is distributed under the terms and conditions of the GNU General Public Lince.
--
--
-- ELEMENTS:
--    procedure wr_chk_val: writes a value, reads it back an checks if it's the same
--    procedure wr_val: writes a value
--    procedure rd_val: reads a value
--    procedure chk_val: checks (after read) a value
 
library IEEE;
use IEEE.std_logic_1164.all;
 
library wb_tk;
use wb_tk.technology.all;
 
package wb_test is
        procedure wr_chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                constant data: in STD_LOGIC_VECTOR
        );
        procedure wr_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                constant data: in STD_LOGIC_VECTOR
        );
        procedure rd_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                variable data: out STD_LOGIC_VECTOR
        );
        procedure chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                constant data: in STD_LOGIC_VECTOR
        );
 
 
        procedure wr_chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        );
        procedure wr_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        );
        procedure rd_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                variable data: out STD_LOGIC_VECTOR
        );
        procedure chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        );
end wb_test;
 
 
package body wb_test is
        procedure wr_chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                constant data: in STD_LOGIC_VECTOR
        ) is
                variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
                variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
        begin
                adr_i <= adr_zero;
                dat_i <= dat_undef;
                stb_i <= '0';
                we_i <= '0';
                cyc_i <= '0';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                adr_i <= addr;
                dat_i <= data;
                cyc_i <= '1';
                stb_i <= '1';
                we_i <= '1';
                wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
                adr_i <= adr_zero;
                dat_i <= dat_undef;
                cyc_i <= '0';
                stb_i <= '0';
                we_i <= '0';
                wait until clk_i'EVENT and clk_i = '1';
                adr_i <= addr;
                dat_i <= dat_undef;
                cyc_i <= '1';
                stb_i <= '1';
                we_i <= '0';
                wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
                assert dat_o = data report "Value does not match!" severity ERROR;
                adr_i <= adr_zero;
                stb_i <= '0';
                cyc_i <= '0';
        end;
 
        procedure wr_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                constant data: in STD_LOGIC_VECTOR
        ) is
                variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
                variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
        begin
                adr_i <= adr_zero;
                dat_i <= dat_undef;
                stb_i <= '0';
                we_i <= '0';
                cyc_i <= '0';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                adr_i <= addr;
                dat_i <= data;
                cyc_i <= '1';
                stb_i <= '1';
                we_i <= '1';
                wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
                adr_i <= adr_zero;
                dat_i <= dat_undef;
                cyc_i <= '0';
                stb_i <= '0';
                we_i <= '0';
        end;
 
        procedure rd_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                variable data: out STD_LOGIC_VECTOR
        ) is
                variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
                variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
        begin
                adr_i <= adr_zero;
                dat_i <= dat_undef;
                cyc_i <= '0';
                stb_i <= '0';
                we_i <= '0';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                adr_i <= addr;
                dat_i <= dat_undef;
                cyc_i <= '1';
                stb_i <= '1';
                we_i <= '0';
                wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
                data := dat_o;
                adr_i <= adr_zero;
                stb_i <= '0';
                cyc_i <= '0';
        end;
 
        procedure chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                constant data: in STD_LOGIC_VECTOR
        ) is
                variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
                variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
        begin
                adr_i <= adr_zero;
                dat_i <= dat_undef;
                cyc_i <= '0';
                stb_i <= '0';
                we_i <= '0';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                adr_i <= addr;
                dat_i <= dat_undef;
                cyc_i <= '1';
                stb_i <= '1';
                we_i <= '0';
                wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
                assert dat_o = data report "Value does not match!" severity ERROR;
                adr_i <= adr_zero;
                stb_i <= '0';
                cyc_i <= '0';
        end;
 
        procedure wr_chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        ) is
                variable sadr: std_logic_vector(adr_i'RANGE);
        begin
                sadr := to_std_logic_vector(addr,adr_i'HIGH+1);
                wr_chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
        end;
        procedure wr_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        ) is
                variable sadr: std_logic_vector(adr_i'RANGE);
        begin
                sadr := to_std_logic_vector(addr,adr_i'HIGH+1);
                wr_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
        end;
        procedure rd_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                variable data: out STD_LOGIC_VECTOR
        ) is
                variable sadr: std_logic_vector(adr_i'RANGE);
        begin
                sadr := to_std_logic_vector(addr,adr_i'HIGH+1);
                rd_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
        end;
        procedure chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        ) is
                variable sadr: std_logic_vector(adr_i'RANGE);
        begin
                sadr := to_std_logic_vector(addr,adr_i'HIGH+1);
                chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
        end;
 
end wb_test;
 

Line No.	Rev	Author	Line
1	4	tantos	`--`
2			`-- Wishbone bus tester utilities.`
3			`--`
4			`-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/04/17`
5			`-- This code is distributed under the terms and conditions of the GNU General Public Lince.`
6			`--`
7			`--`
8			`-- ELEMENTS:`
9			`-- procedure wr_chk_val: writes a value, reads it back an checks if it's the same`
10			`-- procedure wr_val: writes a value`
11			`-- procedure rd_val: reads a value`
12			`-- procedure chk_val: checks (after read) a value`
13
14			`library IEEE;`
15			`use IEEE.std_logic_1164.all;`
16
17	6	tantos	`library wb_tk;`
18			`use wb_tk.technology.all;`
19
20	4	tantos	`package wb_test is`
21			`procedure wr_chk_val(`
22			`signal clk_i: in STD_LOGIC;`
23			`signal adr_i: out STD_LOGIC_VECTOR;`
24			`signal dat_o: in STD_LOGIC_VECTOR;`
25			`signal dat_i: out STD_LOGIC_VECTOR;`
26			`signal we_i: out STD_LOGIC;`
27			`signal cyc_i: out std_logic;`
28			`signal stb_i: out STD_LOGIC;`
29			`signal ack_o: in STD_LOGIC;`
30			`constant addr: in STD_LOGIC_VECTOR;`
31			`constant data: in STD_LOGIC_VECTOR`
32			`);`
33			`procedure wr_val(`
34			`signal clk_i: in STD_LOGIC;`
35			`signal adr_i: out STD_LOGIC_VECTOR;`
36			`signal dat_o: in STD_LOGIC_VECTOR;`
37			`signal dat_i: out STD_LOGIC_VECTOR;`
38			`signal we_i: out STD_LOGIC;`
39			`signal cyc_i: out std_logic;`
40			`signal stb_i: out STD_LOGIC;`
41			`signal ack_o: in STD_LOGIC;`
42			`constant addr: in STD_LOGIC_VECTOR;`
43			`constant data: in STD_LOGIC_VECTOR`
44			`);`
45			`procedure rd_val(`
46			`signal clk_i: in STD_LOGIC;`
47			`signal adr_i: out STD_LOGIC_VECTOR;`
48			`signal dat_o: in STD_LOGIC_VECTOR;`
49			`signal dat_i: out STD_LOGIC_VECTOR;`
50			`signal we_i: out STD_LOGIC;`
51			`signal cyc_i: out std_logic;`
52			`signal stb_i: out STD_LOGIC;`
53			`signal ack_o: in STD_LOGIC;`
54			`constant addr: in STD_LOGIC_VECTOR;`
55			`variable data: out STD_LOGIC_VECTOR`
56			`);`
57			`procedure chk_val(`
58			`signal clk_i: in STD_LOGIC;`
59			`signal adr_i: out STD_LOGIC_VECTOR;`
60			`signal dat_o: in STD_LOGIC_VECTOR;`
61			`signal dat_i: out STD_LOGIC_VECTOR;`
62			`signal we_i: out STD_LOGIC;`
63			`signal cyc_i: out std_logic;`
64			`signal stb_i: out STD_LOGIC;`
65			`signal ack_o: in STD_LOGIC;`
66			`constant addr: in STD_LOGIC_VECTOR;`
67			`constant data: in STD_LOGIC_VECTOR`
68			`);`
69	5	tantos
70
71			`procedure wr_chk_val(`
72			`signal clk_i: in STD_LOGIC;`
73			`signal adr_i: out STD_LOGIC_VECTOR;`
74			`signal dat_o: in STD_LOGIC_VECTOR;`
75			`signal dat_i: out STD_LOGIC_VECTOR;`
76			`signal we_i: out STD_LOGIC;`
77			`signal cyc_i: out std_logic;`
78			`signal stb_i: out STD_LOGIC;`
79			`signal ack_o: in STD_LOGIC;`
80			`constant addr: in integer;`
81			`constant data: in STD_LOGIC_VECTOR`
82			`);`
83			`procedure wr_val(`
84			`signal clk_i: in STD_LOGIC;`
85			`signal adr_i: out STD_LOGIC_VECTOR;`
86			`signal dat_o: in STD_LOGIC_VECTOR;`
87			`signal dat_i: out STD_LOGIC_VECTOR;`
88			`signal we_i: out STD_LOGIC;`
89			`signal cyc_i: out std_logic;`
90			`signal stb_i: out STD_LOGIC;`
91			`signal ack_o: in STD_LOGIC;`
92			`constant addr: in integer;`
93			`constant data: in STD_LOGIC_VECTOR`
94			`);`
95			`procedure rd_val(`
96			`signal clk_i: in STD_LOGIC;`
97			`signal adr_i: out STD_LOGIC_VECTOR;`
98			`signal dat_o: in STD_LOGIC_VECTOR;`
99			`signal dat_i: out STD_LOGIC_VECTOR;`
100			`signal we_i: out STD_LOGIC;`
101			`signal cyc_i: out std_logic;`
102			`signal stb_i: out STD_LOGIC;`
103			`signal ack_o: in STD_LOGIC;`
104			`constant addr: in integer;`
105			`variable data: out STD_LOGIC_VECTOR`
106			`);`
107			`procedure chk_val(`
108			`signal clk_i: in STD_LOGIC;`
109			`signal adr_i: out STD_LOGIC_VECTOR;`
110			`signal dat_o: in STD_LOGIC_VECTOR;`
111			`signal dat_i: out STD_LOGIC_VECTOR;`
112			`signal we_i: out STD_LOGIC;`
113			`signal cyc_i: out std_logic;`
114			`signal stb_i: out STD_LOGIC;`
115			`signal ack_o: in STD_LOGIC;`
116			`constant addr: in integer;`
117			`constant data: in STD_LOGIC_VECTOR`
118			`);`
119	4	tantos	`end wb_test;`
120
121
122			`package body wb_test is`
123	6	tantos	`procedure wr_chk_val(`
124			`signal clk_i: in STD_LOGIC;`
125			`signal adr_i: out STD_LOGIC_VECTOR;`
126			`signal dat_o: in STD_LOGIC_VECTOR;`
127			`signal dat_i: out STD_LOGIC_VECTOR;`
128			`signal we_i: out STD_LOGIC;`
129			`signal cyc_i: out std_logic;`
130			`signal stb_i: out STD_LOGIC;`
131			`signal ack_o: in STD_LOGIC;`
132			`constant addr: in STD_LOGIC_VECTOR;`
133			`constant data: in STD_LOGIC_VECTOR`
134			`) is`
135			`variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');`
136			`variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');`
137			`begin`
138			`adr_i <= adr_zero;`
139			`dat_i <= dat_undef;`
140			`stb_i <= '0';`
141			`we_i <= '0';`
142			`cyc_i <= '0';`
143			`wait until clk_i'EVENT and clk_i = '1';`
144			`wait until clk_i'EVENT and clk_i = '1';`
145			`wait until clk_i'EVENT and clk_i = '1';`
146			`adr_i <= addr;`
147			`dat_i <= data;`
148			`cyc_i <= '1';`
149			`stb_i <= '1';`
150			`we_i <= '1';`
151			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
152			`adr_i <= adr_zero;`
153			`dat_i <= dat_undef;`
154			`cyc_i <= '0';`
155			`stb_i <= '0';`
156			`we_i <= '0';`
157			`wait until clk_i'EVENT and clk_i = '1';`
158			`adr_i <= addr;`
159			`dat_i <= dat_undef;`
160			`cyc_i <= '1';`
161			`stb_i <= '1';`
162			`we_i <= '0';`
163			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
164			`assert dat_o = data report "Value does not match!" severity ERROR;`
165			`adr_i <= adr_zero;`
166			`stb_i <= '0';`
167			`cyc_i <= '0';`
168			`end;`
169	4	tantos
170	6	tantos	`procedure wr_val(`
171			`signal clk_i: in STD_LOGIC;`
172			`signal adr_i: out STD_LOGIC_VECTOR;`
173			`signal dat_o: in STD_LOGIC_VECTOR;`
174			`signal dat_i: out STD_LOGIC_VECTOR;`
175			`signal we_i: out STD_LOGIC;`
176			`signal cyc_i: out std_logic;`
177			`signal stb_i: out STD_LOGIC;`
178			`signal ack_o: in STD_LOGIC;`
179			`constant addr: in STD_LOGIC_VECTOR;`
180			`constant data: in STD_LOGIC_VECTOR`
181			`) is`
182			`variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');`
183			`variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');`
184			`begin`
185			`adr_i <= adr_zero;`
186			`dat_i <= dat_undef;`
187			`stb_i <= '0';`
188			`we_i <= '0';`
189			`cyc_i <= '0';`
190			`wait until clk_i'EVENT and clk_i = '1';`
191			`wait until clk_i'EVENT and clk_i = '1';`
192			`wait until clk_i'EVENT and clk_i = '1';`
193			`adr_i <= addr;`
194			`dat_i <= data;`
195			`cyc_i <= '1';`
196			`stb_i <= '1';`
197			`we_i <= '1';`
198			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
199			`adr_i <= adr_zero;`
200			`dat_i <= dat_undef;`
201			`cyc_i <= '0';`
202			`stb_i <= '0';`
203			`we_i <= '0';`
204			`end;`
205
206			`procedure rd_val(`
207			`signal clk_i: in STD_LOGIC;`
208			`signal adr_i: out STD_LOGIC_VECTOR;`
209			`signal dat_o: in STD_LOGIC_VECTOR;`
210			`signal dat_i: out STD_LOGIC_VECTOR;`
211			`signal we_i: out STD_LOGIC;`
212			`signal cyc_i: out std_logic;`
213			`signal stb_i: out STD_LOGIC;`
214			`signal ack_o: in STD_LOGIC;`
215			`constant addr: in STD_LOGIC_VECTOR;`
216			`variable data: out STD_LOGIC_VECTOR`
217			`) is`
218			`variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');`
219			`variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');`
220			`begin`
221			`adr_i <= adr_zero;`
222			`dat_i <= dat_undef;`
223			`cyc_i <= '0';`
224			`stb_i <= '0';`
225			`we_i <= '0';`
226			`wait until clk_i'EVENT and clk_i = '1';`
227			`wait until clk_i'EVENT and clk_i = '1';`
228			`wait until clk_i'EVENT and clk_i = '1';`
229			`adr_i <= addr;`
230			`dat_i <= dat_undef;`
231			`cyc_i <= '1';`
232			`stb_i <= '1';`
233			`we_i <= '0';`
234			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
235			`data := dat_o;`
236			`adr_i <= adr_zero;`
237			`stb_i <= '0';`
238			`cyc_i <= '0';`
239			`end;`
240
241			`procedure chk_val(`
242			`signal clk_i: in STD_LOGIC;`
243			`signal adr_i: out STD_LOGIC_VECTOR;`
244			`signal dat_o: in STD_LOGIC_VECTOR;`
245			`signal dat_i: out STD_LOGIC_VECTOR;`
246			`signal we_i: out STD_LOGIC;`
247			`signal cyc_i: out std_logic;`
248			`signal stb_i: out STD_LOGIC;`
249			`signal ack_o: in STD_LOGIC;`
250			`constant addr: in STD_LOGIC_VECTOR;`
251			`constant data: in STD_LOGIC_VECTOR`
252			`) is`
253			`variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');`
254			`variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');`
255			`begin`
256			`adr_i <= adr_zero;`
257			`dat_i <= dat_undef;`
258			`cyc_i <= '0';`
259			`stb_i <= '0';`
260			`we_i <= '0';`
261			`wait until clk_i'EVENT and clk_i = '1';`
262			`wait until clk_i'EVENT and clk_i = '1';`
263			`wait until clk_i'EVENT and clk_i = '1';`
264			`adr_i <= addr;`
265			`dat_i <= dat_undef;`
266			`cyc_i <= '1';`
267			`stb_i <= '1';`
268			`we_i <= '0';`
269			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
270			`assert dat_o = data report "Value does not match!" severity ERROR;`
271			`adr_i <= adr_zero;`
272			`stb_i <= '0';`
273			`cyc_i <= '0';`
274			`end;`
275
276	5	tantos	`procedure wr_chk_val(`
277			`signal clk_i: in STD_LOGIC;`
278			`signal adr_i: out STD_LOGIC_VECTOR;`
279			`signal dat_o: in STD_LOGIC_VECTOR;`
280			`signal dat_i: out STD_LOGIC_VECTOR;`
281			`signal we_i: out STD_LOGIC;`
282			`signal cyc_i: out std_logic;`
283			`signal stb_i: out STD_LOGIC;`
284			`signal ack_o: in STD_LOGIC;`
285			`constant addr: in integer;`
286			`constant data: in STD_LOGIC_VECTOR`
287			`) is`
288	6	tantos	`variable sadr: std_logic_vector(adr_i'RANGE);`
289	5	tantos	`begin`
290	6	tantos	`sadr := to_std_logic_vector(addr,adr_i'HIGH+1);`
291			`wr_chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);`
292			`end;`
293	5	tantos	`procedure wr_val(`
294			`signal clk_i: in STD_LOGIC;`
295			`signal adr_i: out STD_LOGIC_VECTOR;`
296			`signal dat_o: in STD_LOGIC_VECTOR;`
297			`signal dat_i: out STD_LOGIC_VECTOR;`
298			`signal we_i: out STD_LOGIC;`
299			`signal cyc_i: out std_logic;`
300			`signal stb_i: out STD_LOGIC;`
301			`signal ack_o: in STD_LOGIC;`
302			`constant addr: in integer;`
303			`constant data: in STD_LOGIC_VECTOR`
304			`) is`
305	6	tantos	`variable sadr: std_logic_vector(adr_i'RANGE);`
306	5	tantos	`begin`
307	6	tantos	`sadr := to_std_logic_vector(addr,adr_i'HIGH+1);`
308			`wr_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);`
309			`end;`
310	5	tantos	`procedure rd_val(`
311			`signal clk_i: in STD_LOGIC;`
312			`signal adr_i: out STD_LOGIC_VECTOR;`
313			`signal dat_o: in STD_LOGIC_VECTOR;`
314			`signal dat_i: out STD_LOGIC_VECTOR;`
315			`signal we_i: out STD_LOGIC;`
316			`signal cyc_i: out std_logic;`
317			`signal stb_i: out STD_LOGIC;`
318			`signal ack_o: in STD_LOGIC;`
319			`constant addr: in integer;`
320			`variable data: out STD_LOGIC_VECTOR`
321			`) is`
322	6	tantos	`variable sadr: std_logic_vector(adr_i'RANGE);`
323	5	tantos	`begin`
324	6	tantos	`sadr := to_std_logic_vector(addr,adr_i'HIGH+1);`
325			`rd_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);`
326			`end;`
327	5	tantos	`procedure chk_val(`
328			`signal clk_i: in STD_LOGIC;`
329			`signal adr_i: out STD_LOGIC_VECTOR;`
330			`signal dat_o: in STD_LOGIC_VECTOR;`
331			`signal dat_i: out STD_LOGIC_VECTOR;`
332			`signal we_i: out STD_LOGIC;`
333			`signal cyc_i: out std_logic;`
334			`signal stb_i: out STD_LOGIC;`
335			`signal ack_o: in STD_LOGIC;`
336			`constant addr: in integer;`
337			`constant data: in STD_LOGIC_VECTOR`
338			`) is`
339	6	tantos	`variable sadr: std_logic_vector(adr_i'RANGE);`
340	5	tantos	`begin`
341	6	tantos	`sadr := to_std_logic_vector(addr,adr_i'HIGH+1);`
342			`chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);`
343			`end;`
344	5	tantos
345	6	tantos	`end wb_test;`
346

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