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<link REL="stylesheet" TYPE="text/css" HREF="/people/tantos/styles.css">
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<h1>WisboneTK</h1>
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<h2>WishboneTK output register</h2>
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<h3>Description</h3>
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<strong>WishboneTK output register</strong> is a parametrized output register with read-back support. It is 100% Wishbone compatible
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with the <a href="wb_extensions.shtml">WishboneTK extensions</a>. The bus-width and the output width can be configured separately.
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Output width can be larger than the bus size. In that case address signals should be used access various parts of the
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however the bus width is required to be bigger than the output width.
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<h3>Wishbone datasheet</h3>
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<table border>
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<tr><th>Description</th><th>Specification</th></tr>
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<tr><td>General Description </td><td>Output register with readback support.</td></tr>
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<tr><td>Supported cycles </td><td>Slave read/write<br>Slave block read/write<br>Slave rmw</td></tr>
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<tr><td>Data port size </td><td>variable</td></tr>
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<tr><td>Data port granularity </td><td>8 bits</td></tr>
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<tr><td>Data port maximum operand size </td><td>same as bus size</td></tr>
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<tr><td>Data transfer ordering </td><td>n/a</td></tr>
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<tr><td>Data transfer sequencing </td><td>n/a</td></tr>
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<tr><td>Supported signal list and cross reference to equivalent Wishbone signals</td><td>
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<table width="100%">
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<tr><th>Signal name</th><th>Wishbone equiv.</th></tr>
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<tr><td>CLK_I </td><td>CLK_I</td></tr>
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<tr><td>RST_I </td><td>RST_I</td></tr>
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<tr><td>CYC_I </td><td>CYC_I</td></tr>
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<tr><td>STB_I </td><td>STB_I</td></tr>
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<tr><td>WE_I </td><td>WE_I </td></tr>
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<tr><td>ACK_O </td><td>ACK_O</td></tr>
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<tr><td>SEL_I(..) </td><td>SEL_I()</td></tr>
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<tr><td>ADR_I(..) </td><td>ADR_I()</td></tr>
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<tr><td>DAT_I() </td><td>DAT_I()</td></tr>
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<tr><td>DAT_O() </td><td>DAT_O()</td></tr>
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</table>
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</table>
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<h3>Parameter description</h3>
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<table border>
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<tr><th>Parameter name</th><th>Description</th></tr>
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<tr><td>width</td><td>Number of bits in the output register</td></tr>
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<tr><td>bus_width</td><td>Size of the data-bus</td></tr>
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<tr><td>offset</td><td>Bit-offset from where the output bits start within the data</td></tr>
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</table>
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<h3>Signal description</h3>
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<table border>
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<tr><th>Signal name </th><th>Description</th></tr>
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<tr><td>CLK_I </td><td>Wishbone clock signal</td></tr>
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<tr><td>RST_I </td><td>Wishbone reset signal</td></tr>
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<tr><td>CYC_I </td><td>Wishbone cycle signal. High value frames blocks of access</td></tr>
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<tr><td>STB_I </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>
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<tr><td>WE_I </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>
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<tr><td>ACK_O </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>
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<tr><td>ACK_OI </td><td>WhisboneTK acknowledge chain input signal</td></tr>
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<tr><td>SEL_I(bus_width/8-1..0) </td><td>Wishbone byte-selection signals</td></tr>
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<tr><td>ADR_I(addr_width<sup>*</sup>-1..0) </td><td>Wishbone address bus signals</td></tr>
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<tr><td>DAT_I(bus_width-1..0) </td><td>Wishbone data bus input (to slave direction) signals</td></tr>
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<tr><td>DAT_O(bus_width-1..0) </td><td>Wishbone data bus output (to master direction) signals</td></tr>
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<tr><td>DAT_OI(bus_width-1..0) </td><td>WhisboneTK data bus chain input signal</td></tr>
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<tr><td>RST_VAL(width-1..0) </td><td>Value written to the register upon reset</td></tr>
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<tr><td>Q(width-1..0) </td><td>Output value of the register</td></tr>
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</td></tr></table>
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<p>
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<strong>* addr_with:</strong> size2bits((width+offset+bus_width-1)/bus_width)-1.
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<h2>Author & Maintainer</h2>
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<p>
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<a href="/people/tantos">Andras Tantos</a>
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