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[/] [wb_to_amba/] [trunk/] [sim/] [models/] [bfm_ahb.v] - Blame information for rev 2

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//
//
//
 
`timescale 1ns / 100ps
 
 
 
module bfm_ahb(
                  output          hclk,
                  output          hresetn,
                  output  [31:0]  haddr,
                  output  [1:0]   htrans,
                  output          hwrite,
                  output  [2:0]   hsize,
                  output  [2:0]   hburst,
                  output  [3:0]   hprot,
                  output  [31:0]  hwdata,
                  output          hsel,
 
                  input  [31:0]   hrdata,
                  output          hready_in,
                  input           hready_out,
                  input  [1:0]    hresp,
 
                  input           bfm_clk,
                  input           bfm_reset
                );
 
  parameter LOG_LEVEL = 3;
 
 
  // -----------------------------
  //  
 
  reg read_error;
 
  reg hready_out_wait_r;
 
  reg [31:0]  haddr_r;
  reg  [1:0]  htrans_r;
  reg         hwrite_r;
  reg  [2:0]  hsize_r;
  reg  [2:0]  hburst_r;
  reg  [3:0]  hprot_r;
  reg  [31:0] hwdata_r;
  reg         hsel_r;
  reg         hready_in_r;
 
  assign haddr  = haddr_r;
  assign htrans = htrans_r;
  assign hwrite = hwrite_r;
  assign hsize = hsize_r;
  assign hburst = hburst_r;
  assign hprot = hprot_r;
  assign hwdata = hwdata_r;
  assign hsel = hsel_r;
  assign hready_in = hready_in_r;
 
 
  // -----------------------------
  //  initialize the bus
  initial
    begin
      read_error <= 0;
      bfm_ahb_default;
    end
 
 
  // -----------------------------
  //  addr_control_default
  task addr_control_default;
    begin
    haddr_r <= 32'hxxxxxxxx;
    htrans_r <= 2'bxx;
    hwrite_r <= 1'bx;
    hsize_r <= 3'bxxx;
    hburst_r <= 3'bxxx;
    hprot_r <= 4'bxxxx;
    end
  endtask
 
 
  // -----------------------------
  //  bfm_ahb_default
  task bfm_ahb_default;
    begin
    hready_out_wait_r <= 1'b0;
 
    addr_control_default();
 
    hwdata_r <= 32'hxxxxxxxx;
    hsel_r <= 1'b0;
    hready_in_r <= 1'b0;
    end
  endtask
 
  // -----------------------------
  //  bfm_ahb_write32
  task bfm_ahb_write32;
 
    input  [31:0] target_addr;
    input  [31:0] target_data;
 
    begin
 
      if(LOG_LEVEL >= 3)
        $display( "-+- bfm_ahb_write32: write 0x%x to 0x%x.", target_data, target_addr);
 
      @(posedge hclk);
      #1;
 
      haddr_r <= target_addr;
      hwdata_r <= target_data;
      htrans_r <= 2'b10;
      hwrite_r <= 1'b1;
      hsize_r <= 3'b010;
      hburst_r <= 3'b000;
      hprot_r <= 4'b0000;
      hsel_r <= 1'b1;
      hready_in_r <= 1'b1;
 
      @(negedge hclk);
      @(negedge hclk);
 
      hready_in_r = 1'b0;
      hsel_r <= 1'b0;
 
      addr_control_default();
 
      hready_out_wait_r <= 1'b1;
      wait(hready_out);
      hready_out_wait_r <= 1'b0;
 
      @(posedge hclk);
      bfm_ahb_default;
 
    end
  endtask
 
 
  // -----------------------------
  //  bfm_ahb_read32
  task bfm_ahb_read32;
 
    input  [31:0] target_addr;
    input         check_data;
    input  [31:0] data_compare;
 
    reg    [31:0] read_data_r;
 
    begin
 
      @(posedge hclk);
      #1;
 
      haddr_r <= target_addr;
      htrans_r <= 2'b10;
      hwrite_r <= 1'b0;
      hsize_r <= 3'b010;
      hburst_r <= 3'b000;
      hprot_r <= 4'b0000;
      hsel_r <= 1'b1;
      hready_in_r <= 1'b1;
 
     @(negedge hclk);
     @(negedge hclk);
 
      hready_in_r = 1'b0;
      hsel_r <= 1'b0;
 
      addr_control_default();
 
      hready_out_wait_r <= 1'b1;
      wait(hready_out);
      hready_out_wait_r <= 1'b0;
 
      @(posedge hclk);
      read_data_r <= hrdata;
 
      @(posedge hclk);
      bfm_ahb_default;
 
      if(LOG_LEVEL >= 3)
        $display( "-+- bfm_ahb_read32:  read 0x%x from 0x%x.", read_data_r, target_addr);
 
      if( LOG_LEVEL >= 1 & check_data & (data_compare !== read_data_r) )
        begin
          read_error = 1'b1;
          $display( "-!- bfm_ahb_read32:  Data mismatch. Should be 0x%x.", data_compare);
        end
 
    end
  endtask
 
 
  // -----------------------------
  //  bfm_ahb_write16
  task bfm_ahb_write16;
 
    input  [31:0] target_addr;
    input  [15:0] target_data;
 
    reg [15:0] target_data_lo;
    reg [15:0] target_data_hi;
 
    begin
 
      if(LOG_LEVEL >= 3)
        $display( "-+- bfm_ahb_write16: write 0x%x to 0x%x.", target_data, target_addr);
 
      @(posedge hclk);
      #1;
 
      haddr_r <= target_addr;
 
      target_data_lo = target_addr[1] ? 16'hxxxx : target_data;
      target_data_hi = target_addr[1] ? target_data : 16'hxxxx;
      hwdata_r <= { target_data_hi, target_data_lo };
 
      htrans_r <= 2'b10;
      hwrite_r <= 1'b1;
      hsize_r <= 3'b001;
      hburst_r <= 3'b000;
      hprot_r <= 4'b0000;
      hsel_r <= 1'b1;
      hready_in_r <= 1'b1;
 
      @(negedge hclk);
      @(negedge hclk);
 
      hready_in_r = 1'b0;
      hsel_r <= 1'b0;
 
      addr_control_default();
 
      hready_out_wait_r <= 1'b1;
      wait(hready_out);
      hready_out_wait_r <= 1'b0;
 
      @(posedge hclk);
      bfm_ahb_default;
 
    end
  endtask
 
 
  // -----------------------------
  //  bfm_ahb_read16
  task bfm_ahb_read16;
 
    input  [31:0] target_addr;
    input         check_data;
    input  [15:0] data_compare;
 
    reg    [15:0] read_data_r;
 
    begin
 
      @(posedge hclk);
      #1;
 
      haddr_r <= target_addr;
      htrans_r <= 2'b10;
      hwrite_r <= 1'b0;
      hsize_r <= 3'b001;
      hburst_r <= 3'b000;
      hprot_r <= 4'b0000;
      hsel_r <= 1'b1;
      hready_in_r <= 1'b1;
 
     @(negedge hclk);
     @(negedge hclk);
 
      hready_in_r = 1'b0;
      hsel_r <= 1'b0;
 
      addr_control_default();
 
      hready_out_wait_r <= 1'b1;
      wait(hready_out);
      hready_out_wait_r <= 1'b0;
 
      @(posedge hclk);
      read_data_r <= target_addr[1] ? hrdata[31:16] : hrdata[15:0];
 
      @(posedge hclk);
      bfm_ahb_default;
 
      if(LOG_LEVEL >= 3)
        $display( "-+- bfm_ahb_read16:  read 0x%x from 0x%x.", read_data_r, target_addr);
 
      if( LOG_LEVEL >= 1 & check_data & (data_compare !== read_data_r) )
        begin
          read_error = 1'b1;
          $display( "-!- bfm_ahb_read32:  Data mismatch. Should be 0x%x.", data_compare);
        end
 
    end
  endtask
 
    // -----------------------------
  //  bfm_ahb_write8
  task bfm_ahb_write8;
 
    input  [31:0] target_addr;
    input  [7:0] target_data;
 
    reg  [7:0] target_data_0;
    reg  [7:0] target_data_1;
    reg  [7:0] target_data_2;
    reg  [7:0] target_data_3;
 
    begin
 
      if(LOG_LEVEL >= 3)
        $display( "-+- bfm_ahb_write8: write 0x%x to 0x%x.", target_data, target_addr);
 
      @(posedge hclk);
      #1;
 
      haddr_r <= target_addr;
 
      target_data_0 = (target_addr[1:0] == 2'b00) ? target_data : 8'hxxxx;
      target_data_1 = (target_addr[1:0] == 2'b01) ? target_data : 8'hxxxx;
      target_data_2 = (target_addr[1:0] == 2'b10) ? target_data : 8'hxxxx;
      target_data_3 = (target_addr[1:0] == 2'b11) ? target_data : 8'hxxxx;
      hwdata_r <= { target_data_3, target_data_2, target_data_1, target_data_0 };
 
      htrans_r <= 2'b10;
      hwrite_r <= 1'b1;
      hsize_r <= 3'b000;
      hburst_r <= 3'b000;
      hprot_r <= 4'b0000;
      hsel_r <= 1'b1;
      hready_in_r <= 1'b1;
 
      @(negedge hclk);
      @(negedge hclk);
 
      hready_in_r = 1'b0;
      hsel_r <= 1'b0;
 
      addr_control_default();
 
      hready_out_wait_r <= 1'b1;
      wait(hready_out);
      hready_out_wait_r <= 1'b0;
 
      @(posedge hclk);
      bfm_ahb_default;
 
    end
  endtask
 
 
  // -----------------------------
  //  bfm_ahb_read8
  task bfm_ahb_read8;
 
    input  [31:0] target_addr;
    input         check_data;
    input  [7:0] data_compare;
 
    reg    [7:0] read_data_r;
 
    begin
 
      @(posedge hclk);
      #1;
 
      haddr_r <= target_addr;
      htrans_r <= 2'b10;
      hwrite_r <= 1'b0;
      hsize_r <= 3'b000;
      hburst_r <= 3'b000;
      hprot_r <= 4'b0000;
      hsel_r <= 1'b1;
      hready_in_r <= 1'b1;
 
     @(negedge hclk);
     @(negedge hclk);
 
      hready_in_r = 1'b0;
      hsel_r <= 1'b0;
 
      addr_control_default();
 
      hready_out_wait_r <= 1'b1;
      wait(hready_out);
      hready_out_wait_r <= 1'b0;
 
      @(posedge hclk);
      case( target_addr[1:0] )
        2'b00:  read_data_r = hrdata[7:0];
        2'b01:  read_data_r = hrdata[15:8];
        2'b10:  read_data_r = hrdata[23:16];
        2'b11:  read_data_r = hrdata[31:24];
      endcase
 
      @(posedge hclk);
      bfm_ahb_default;
 
      if(LOG_LEVEL >= 3)
        $display( "-+- bfm_ahb_read8:  read 0x%x from 0x%x.", read_data_r, target_addr);
 
      if( LOG_LEVEL >= 1 & check_data & (data_compare !== read_data_r) )
        begin
          read_error = 1'b1;
          $display( "-!- bfm_ahb_read8:  Data mismatch. Should be 0x%x.", data_compare);
        end
 
    end
  endtask
 
 
  // -----------------------------
  //  outputs
 
  assign hclk     = bfm_clk;
  assign hresetn  = ~bfm_reset;
 
 
endmodule
 
 

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[/] [wb_to_amba/] [trunk/] [sim/] [models/] [bfm_ahb.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	qaztronic	`//`
2			`//`
3			`//`
4
5			`timescale 1ns / 100ps
6
7
8
9			`module bfm_ahb(`
10			`output hclk,`
11			`output hresetn,`
12			`output [31:0] haddr,`
13			`output [1:0] htrans,`
14			`output hwrite,`
15			`output [2:0] hsize,`
16			`output [2:0] hburst,`
17			`output [3:0] hprot,`
18			`output [31:0] hwdata,`
19			`output hsel,`
20
21			`input [31:0] hrdata,`
22			`output hready_in,`
23			`input hready_out,`
24			`input [1:0] hresp,`
25
26			`input bfm_clk,`
27			`input bfm_reset`
28			`);`
29
30			`parameter LOG_LEVEL = 3;`
31
32
33			`// -----------------------------`
34			`//`
35
36			`reg read_error;`
37
38			`reg hready_out_wait_r;`
39
40			`reg [31:0] haddr_r;`
41			`reg [1:0] htrans_r;`
42			`reg hwrite_r;`
43			`reg [2:0] hsize_r;`
44			`reg [2:0] hburst_r;`
45			`reg [3:0] hprot_r;`
46			`reg [31:0] hwdata_r;`
47			`reg hsel_r;`
48			`reg hready_in_r;`
49
50			`assign haddr = haddr_r;`
51			`assign htrans = htrans_r;`
52			`assign hwrite = hwrite_r;`
53			`assign hsize = hsize_r;`
54			`assign hburst = hburst_r;`
55			`assign hprot = hprot_r;`
56			`assign hwdata = hwdata_r;`
57			`assign hsel = hsel_r;`
58			`assign hready_in = hready_in_r;`
59
60
61			`// -----------------------------`
62			`// initialize the bus`
63			`initial`
64			`begin`
65			`read_error <= 0;`
66			`bfm_ahb_default;`
67			`end`
68
69
70			`// -----------------------------`
71			`// addr_control_default`
72			`task addr_control_default;`
73			`begin`
74			`haddr_r <= 32'hxxxxxxxx;`
75			`htrans_r <= 2'bxx;`
76			`hwrite_r <= 1'bx;`
77			`hsize_r <= 3'bxxx;`
78			`hburst_r <= 3'bxxx;`
79			`hprot_r <= 4'bxxxx;`
80			`end`
81			`endtask`
82
83
84			`// -----------------------------`
85			`// bfm_ahb_default`
86			`task bfm_ahb_default;`
87			`begin`
88			`hready_out_wait_r <= 1'b0;`
89
90			`addr_control_default();`
91
92			`hwdata_r <= 32'hxxxxxxxx;`
93			`hsel_r <= 1'b0;`
94			`hready_in_r <= 1'b0;`
95			`end`
96			`endtask`
97
98			`// -----------------------------`
99			`// bfm_ahb_write32`
100			`task bfm_ahb_write32;`
101
102			`input [31:0] target_addr;`
103			`input [31:0] target_data;`
104
105			`begin`
106
107			`if(LOG_LEVEL >= 3)`
108			`$display( "-+- bfm_ahb_write32: write 0x%x to 0x%x.", target_data, target_addr);`
109
110			`@(posedge hclk);`
111			`#1;`
112
113			`haddr_r <= target_addr;`
114			`hwdata_r <= target_data;`
115			`htrans_r <= 2'b10;`
116			`hwrite_r <= 1'b1;`
117			`hsize_r <= 3'b010;`
118			`hburst_r <= 3'b000;`
119			`hprot_r <= 4'b0000;`
120			`hsel_r <= 1'b1;`
121			`hready_in_r <= 1'b1;`
122
123			`@(negedge hclk);`
124			`@(negedge hclk);`
125
126			`hready_in_r = 1'b0;`
127			`hsel_r <= 1'b0;`
128
129			`addr_control_default();`
130
131			`hready_out_wait_r <= 1'b1;`
132			`wait(hready_out);`
133			`hready_out_wait_r <= 1'b0;`
134
135			`@(posedge hclk);`
136			`bfm_ahb_default;`
137
138			`end`
139			`endtask`
140
141
142			`// -----------------------------`
143			`// bfm_ahb_read32`
144			`task bfm_ahb_read32;`
145
146			`input [31:0] target_addr;`
147			`input check_data;`
148			`input [31:0] data_compare;`
149
150			`reg [31:0] read_data_r;`
151
152			`begin`
153
154			`@(posedge hclk);`
155			`#1;`
156
157			`haddr_r <= target_addr;`
158			`htrans_r <= 2'b10;`
159			`hwrite_r <= 1'b0;`
160			`hsize_r <= 3'b010;`
161			`hburst_r <= 3'b000;`
162			`hprot_r <= 4'b0000;`
163			`hsel_r <= 1'b1;`
164			`hready_in_r <= 1'b1;`
165
166			`@(negedge hclk);`
167			`@(negedge hclk);`
168
169			`hready_in_r = 1'b0;`
170			`hsel_r <= 1'b0;`
171
172			`addr_control_default();`
173
174			`hready_out_wait_r <= 1'b1;`
175			`wait(hready_out);`
176			`hready_out_wait_r <= 1'b0;`
177
178			`@(posedge hclk);`
179			`read_data_r <= hrdata;`
180
181			`@(posedge hclk);`
182			`bfm_ahb_default;`
183
184			`if(LOG_LEVEL >= 3)`
185			`$display( "-+- bfm_ahb_read32: read 0x%x from 0x%x.", read_data_r, target_addr);`
186
187			`if( LOG_LEVEL >= 1 & check_data & (data_compare !== read_data_r) )`
188			`begin`
189			`read_error = 1'b1;`
190			`$display( "-!- bfm_ahb_read32: Data mismatch. Should be 0x%x.", data_compare);`
191			`end`
192
193			`end`
194			`endtask`
195
196
197			`// -----------------------------`
198			`// bfm_ahb_write16`
199			`task bfm_ahb_write16;`
200
201			`input [31:0] target_addr;`
202			`input [15:0] target_data;`
203
204			`reg [15:0] target_data_lo;`
205			`reg [15:0] target_data_hi;`
206
207			`begin`
208
209			`if(LOG_LEVEL >= 3)`
210			`$display( "-+- bfm_ahb_write16: write 0x%x to 0x%x.", target_data, target_addr);`
211
212			`@(posedge hclk);`
213			`#1;`
214
215			`haddr_r <= target_addr;`
216
217			`target_data_lo = target_addr[1] ? 16'hxxxx : target_data;`
218			`target_data_hi = target_addr[1] ? target_data : 16'hxxxx;`
219			`hwdata_r <= { target_data_hi, target_data_lo };`
220
221			`htrans_r <= 2'b10;`
222			`hwrite_r <= 1'b1;`
223			`hsize_r <= 3'b001;`
224			`hburst_r <= 3'b000;`
225			`hprot_r <= 4'b0000;`
226			`hsel_r <= 1'b1;`
227			`hready_in_r <= 1'b1;`
228
229			`@(negedge hclk);`
230			`@(negedge hclk);`
231
232			`hready_in_r = 1'b0;`
233			`hsel_r <= 1'b0;`
234
235			`addr_control_default();`
236
237			`hready_out_wait_r <= 1'b1;`
238			`wait(hready_out);`
239			`hready_out_wait_r <= 1'b0;`
240
241			`@(posedge hclk);`
242			`bfm_ahb_default;`
243
244			`end`
245			`endtask`
246
247
248			`// -----------------------------`
249			`// bfm_ahb_read16`
250			`task bfm_ahb_read16;`
251
252			`input [31:0] target_addr;`
253			`input check_data;`
254			`input [15:0] data_compare;`
255
256			`reg [15:0] read_data_r;`
257
258			`begin`
259
260			`@(posedge hclk);`
261			`#1;`
262
263			`haddr_r <= target_addr;`
264			`htrans_r <= 2'b10;`
265			`hwrite_r <= 1'b0;`
266			`hsize_r <= 3'b001;`
267			`hburst_r <= 3'b000;`
268			`hprot_r <= 4'b0000;`
269			`hsel_r <= 1'b1;`
270			`hready_in_r <= 1'b1;`
271
272			`@(negedge hclk);`
273			`@(negedge hclk);`
274
275			`hready_in_r = 1'b0;`
276			`hsel_r <= 1'b0;`
277
278			`addr_control_default();`
279
280			`hready_out_wait_r <= 1'b1;`
281			`wait(hready_out);`
282			`hready_out_wait_r <= 1'b0;`
283
284			`@(posedge hclk);`
285			`read_data_r <= target_addr[1] ? hrdata[31:16] : hrdata[15:0];`
286
287			`@(posedge hclk);`
288			`bfm_ahb_default;`
289
290			`if(LOG_LEVEL >= 3)`
291			`$display( "-+- bfm_ahb_read16: read 0x%x from 0x%x.", read_data_r, target_addr);`
292
293			`if( LOG_LEVEL >= 1 & check_data & (data_compare !== read_data_r) )`
294			`begin`
295			`read_error = 1'b1;`
296			`$display( "-!- bfm_ahb_read32: Data mismatch. Should be 0x%x.", data_compare);`
297			`end`
298
299			`end`
300			`endtask`
301
302			`// -----------------------------`
303			`// bfm_ahb_write8`
304			`task bfm_ahb_write8;`
305
306			`input [31:0] target_addr;`
307			`input [7:0] target_data;`
308
309			`reg [7:0] target_data_0;`
310			`reg [7:0] target_data_1;`
311			`reg [7:0] target_data_2;`
312			`reg [7:0] target_data_3;`
313
314			`begin`
315
316			`if(LOG_LEVEL >= 3)`
317			`$display( "-+- bfm_ahb_write8: write 0x%x to 0x%x.", target_data, target_addr);`
318
319			`@(posedge hclk);`
320			`#1;`
321
322			`haddr_r <= target_addr;`
323
324			`target_data_0 = (target_addr[1:0] == 2'b00) ? target_data : 8'hxxxx;`
325			`target_data_1 = (target_addr[1:0] == 2'b01) ? target_data : 8'hxxxx;`
326			`target_data_2 = (target_addr[1:0] == 2'b10) ? target_data : 8'hxxxx;`
327			`target_data_3 = (target_addr[1:0] == 2'b11) ? target_data : 8'hxxxx;`
328			`hwdata_r <= { target_data_3, target_data_2, target_data_1, target_data_0 };`
329
330			`htrans_r <= 2'b10;`
331			`hwrite_r <= 1'b1;`
332			`hsize_r <= 3'b000;`
333			`hburst_r <= 3'b000;`
334			`hprot_r <= 4'b0000;`
335			`hsel_r <= 1'b1;`
336			`hready_in_r <= 1'b1;`
337
338			`@(negedge hclk);`
339			`@(negedge hclk);`
340
341			`hready_in_r = 1'b0;`
342			`hsel_r <= 1'b0;`
343
344			`addr_control_default();`
345
346			`hready_out_wait_r <= 1'b1;`
347			`wait(hready_out);`
348			`hready_out_wait_r <= 1'b0;`
349
350			`@(posedge hclk);`
351			`bfm_ahb_default;`
352
353			`end`
354			`endtask`
355
356
357			`// -----------------------------`
358			`// bfm_ahb_read8`
359			`task bfm_ahb_read8;`
360
361			`input [31:0] target_addr;`
362			`input check_data;`
363			`input [7:0] data_compare;`
364
365			`reg [7:0] read_data_r;`
366
367			`begin`
368
369			`@(posedge hclk);`
370			`#1;`
371
372			`haddr_r <= target_addr;`
373			`htrans_r <= 2'b10;`
374			`hwrite_r <= 1'b0;`
375			`hsize_r <= 3'b000;`
376			`hburst_r <= 3'b000;`
377			`hprot_r <= 4'b0000;`
378			`hsel_r <= 1'b1;`
379			`hready_in_r <= 1'b1;`
380
381			`@(negedge hclk);`
382			`@(negedge hclk);`
383
384			`hready_in_r = 1'b0;`
385			`hsel_r <= 1'b0;`
386
387			`addr_control_default();`
388
389			`hready_out_wait_r <= 1'b1;`
390			`wait(hready_out);`
391			`hready_out_wait_r <= 1'b0;`
392
393			`@(posedge hclk);`
394			`case( target_addr[1:0] )`
395			`2'b00: read_data_r = hrdata[7:0];`
396			`2'b01: read_data_r = hrdata[15:8];`
397			`2'b10: read_data_r = hrdata[23:16];`
398			`2'b11: read_data_r = hrdata[31:24];`
399			`endcase`
400
401			`@(posedge hclk);`
402			`bfm_ahb_default;`
403
404			`if(LOG_LEVEL >= 3)`
405			`$display( "-+- bfm_ahb_read8: read 0x%x from 0x%x.", read_data_r, target_addr);`
406
407			`if( LOG_LEVEL >= 1 & check_data & (data_compare !== read_data_r) )`
408			`begin`
409			`read_error = 1'b1;`
410			`$display( "-!- bfm_ahb_read8: Data mismatch. Should be 0x%x.", data_compare);`
411			`end`
412
413			`end`
414			`endtask`
415
416
417			`// -----------------------------`
418			`// outputs`
419
420			`assign hclk = bfm_clk;`
421			`assign hresetn = ~bfm_reset;`
422
423
424			`endmodule`
425
426