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[/] [wb_vga/] [tags/] [a01/] [technology.vhd] - Blame information for rev 8

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--
--  Technology mapping library. ALTERA edition.
--
--  (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
--  This code is distributed under the terms and conditions of the GNU General Public Lince.
--
 
library IEEE;
use IEEE.std_logic_1164.all;
library exemplar;
use exemplar.exemplar_1164.all;
 
package technology is
        function add_one(inp : std_logic_vector) return std_logic_vector;
        function is_zero(inp : std_logic_vector) return boolean;
    function sl(l: std_logic_vector; r: integer) return std_logic_vector;
--      procedure inc(data : inout std_logic_vector);
    function "+"(op_l, op_r: std_logic_vector) return std_logic_vector;
 
        component d_ff is
                port (  d  :  in STD_LOGIC;
                                clk:  in STD_LOGIC;
                        ena:  in STD_LOGIC := '1';
                        clr:  in STD_LOGIC := '0';
                        pre:  in STD_LOGIC := '0';
                                q  :  out STD_LOGIC
                );
        end component;
        component fifo is
                generic (fifo_width : positive;
                                 used_width : positive;
                                 fifo_depth : positive
                );
                port (d_in : in std_logic_vector(fifo_width-1 downto 0);
                          clk : in std_logic;
                          wr : in std_logic;
                          rd : in std_logic;
                          a_clr : in std_logic := '0';
                          s_clr : in std_logic := '0';
                          d_out : out std_logic_vector(fifo_width-1 downto 0);
                          used : out std_logic_vector(used_width-1 downto 0);
                          full : out std_logic;
                          empty : out std_logic
                );
        end component;
end technology;
 
library IEEE;
use IEEE.std_logic_1164.all;
library exemplar;
use exemplar.exemplar_1164.all;
 
package body technology is
    function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is
        begin
                return exemplar_1164."+"(op_l, op_r);
        end;
 
        function add_one(inp : std_logic_vector) return std_logic_vector is
                variable one: std_logic_vector(inp'RANGE) := (others => '0');
        begin
                one(0) := '1';
                return exemplar_1164."+"(inp,one);
        end;
 
        function is_zero(inp : std_logic_vector) return boolean is
                variable zero: std_logic_vector(inp'RANGE) := (others => '0');
        begin
                return (inp = zero);
        end;
 
    function sl(l: std_logic_vector; r: integer) return std_logic_vector is
    begin
        return exemplar_1164.sl(l,r);
    end;
--      procedure inc(data : inout std_logic_vector) is
--      begin
--              data := addone(data);
--      end;
end package body technology;
 
 
library IEEE;
use IEEE.std_logic_1164.all;
 
library exemplar;
use exemplar.exemplar_1164.all;
 
library lpm;
use lpm.all;
 
entity fifo is
        generic (fifo_width : positive;
                         used_width : positive;
                         fifo_depth : positive
        );
        port (d_in : in std_logic_vector(fifo_width-1 downto 0);
                  clk : in std_logic;
                  wr : in std_logic;
                  rd : in std_logic;
                  a_clr : in std_logic := '0';
                  s_clr : in std_logic := '0';
                  d_out : out std_logic_vector(fifo_width-1 downto 0);
                  used : out std_logic_vector(used_width-1 downto 0);
                  full : out std_logic;
                  empty : out std_logic
        );
end fifo;
 
architecture altera of fifo is
        component lpm_fifo
                generic (LPM_WIDTH : positive;
                                 LPM_WIDTHU : positive;
                                 LPM_NUMWORDS : positive;
                                 LPM_SHOWAHEAD : string := "OFF";
                                 LPM_TYPE : string := "LPM_FIFO";
                                 LPM_HINT : string := "UNUSED");
                port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
                          CLOCK : in std_logic;
                          WRREQ : in std_logic;
                          RDREQ : in std_logic;
                          ACLR : in std_logic;
                          SCLR : in std_logic;
                          Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
                          USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
                          FULL : out std_logic;
                          EMPTY : out std_logic);
        end component;
begin
        altera_fifo: lpm_fifo
                generic map (
                        LPM_WIDTH => fifo_width,
                        LPM_WIDTHU => used_width,
                        LPM_NUMWORDS => fifo_depth,
                        LPM_SHOWAHEAD => "OFF",
                        LPM_TYPE => "LPM_FIFO",
                        LPM_HINT => "UNUSED"
                )
                port map (
                        DATA => d_in,
                        CLOCK => clk,
                        WRREQ => wr,
                        RDREQ => rd,
                        ACLR => a_clr,
                        SCLR => s_clr,
                        Q => d_out,
                        USEDW => used,
                        FULL => full,
                        EMPTY => empty
                );
end altera;
 
 
library IEEE;
use IEEE.std_logic_1164.all;
 
library altera_exemplar;
use altera_exemplar.all;
 
entity d_ff is
        port (  d  :  in STD_LOGIC;
                        clk:  in STD_LOGIC;
                ena:  in STD_LOGIC := '1';
                clr:  in STD_LOGIC := '0';
                pre:  in STD_LOGIC := '0';
                        q  :  out STD_LOGIC
        );
end d_ff;
 
architecture altera of d_ff is
        component dffe
        port (  D  :  in STD_LOGIC;
                        CLK:  in STD_LOGIC;
                ENA:  in STD_LOGIC;
                CLRN: in STD_LOGIC;
                PRN:  in STD_LOGIC;
                        Q  :  out STD_LOGIC);
        end component;
        signal clrn,prn: std_logic;
begin
        clrn <= not clr;
        prn <= not pre;
        ff: dffe port map (
                D => d,
                CLK => clk,
                ENA => ena,
                CLRN => clrn,
                PRN => prn,
                Q => q
        );
end altera;
 
-- Sythetizer library. Contains STD_LOGIC arithmetics
 

Line No.	Rev	Author	Line
1	2	tantos	`--`
2			`-- Technology mapping library. ALTERA edition.`
3			`--`
4			`-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31`
5			`-- This code is distributed under the terms and conditions of the GNU General Public Lince.`
6			`--`
7
8			`library IEEE;`
9			`use IEEE.std_logic_1164.all;`
10			`library exemplar;`
11			`use exemplar.exemplar_1164.all;`
12
13			`package technology is`
14			`function add_one(inp : std_logic_vector) return std_logic_vector;`
15			`function is_zero(inp : std_logic_vector) return boolean;`
16			`function sl(l: std_logic_vector; r: integer) return std_logic_vector;`
17			`-- procedure inc(data : inout std_logic_vector);`
18			`function "+"(op_l, op_r: std_logic_vector) return std_logic_vector;`
19
20			`component d_ff is`
21			`port ( d : in STD_LOGIC;`
22			`clk: in STD_LOGIC;`
23			`ena: in STD_LOGIC := '1';`
24			`clr: in STD_LOGIC := '0';`
25			`pre: in STD_LOGIC := '0';`
26			`q : out STD_LOGIC`
27			`);`
28			`end component;`
29			`component fifo is`
30			`generic (fifo_width : positive;`
31			`used_width : positive;`
32			`fifo_depth : positive`
33			`);`
34			`port (d_in : in std_logic_vector(fifo_width-1 downto 0);`
35			`clk : in std_logic;`
36			`wr : in std_logic;`
37			`rd : in std_logic;`
38			`a_clr : in std_logic := '0';`
39			`s_clr : in std_logic := '0';`
40			`d_out : out std_logic_vector(fifo_width-1 downto 0);`
41			`used : out std_logic_vector(used_width-1 downto 0);`
42			`full : out std_logic;`
43			`empty : out std_logic`
44			`);`
45			`end component;`
46			`end technology;`
47
48			`library IEEE;`
49			`use IEEE.std_logic_1164.all;`
50			`library exemplar;`
51			`use exemplar.exemplar_1164.all;`
52
53			`package body technology is`
54			`function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is`
55			`begin`
56			`return exemplar_1164."+"(op_l, op_r);`
57			`end;`
58
59			`function add_one(inp : std_logic_vector) return std_logic_vector is`
60			`variable one: std_logic_vector(inp'RANGE) := (others => '0');`
61			`begin`
62			`one(0) := '1';`
63			`return exemplar_1164."+"(inp,one);`
64			`end;`
65
66			`function is_zero(inp : std_logic_vector) return boolean is`
67			`variable zero: std_logic_vector(inp'RANGE) := (others => '0');`
68			`begin`
69			`return (inp = zero);`
70			`end;`
71
72			`function sl(l: std_logic_vector; r: integer) return std_logic_vector is`
73			`begin`
74			`return exemplar_1164.sl(l,r);`
75			`end;`
76			`-- procedure inc(data : inout std_logic_vector) is`
77			`-- begin`
78			`-- data := addone(data);`
79			`-- end;`
80			`end package body technology;`
81
82
83			`library IEEE;`
84			`use IEEE.std_logic_1164.all;`
85
86			`library exemplar;`
87			`use exemplar.exemplar_1164.all;`
88
89			`library lpm;`
90			`use lpm.all;`
91
92			`entity fifo is`
93			`generic (fifo_width : positive;`
94			`used_width : positive;`
95			`fifo_depth : positive`
96			`);`
97			`port (d_in : in std_logic_vector(fifo_width-1 downto 0);`
98			`clk : in std_logic;`
99			`wr : in std_logic;`
100			`rd : in std_logic;`
101			`a_clr : in std_logic := '0';`
102			`s_clr : in std_logic := '0';`
103			`d_out : out std_logic_vector(fifo_width-1 downto 0);`
104			`used : out std_logic_vector(used_width-1 downto 0);`
105			`full : out std_logic;`
106			`empty : out std_logic`
107			`);`
108			`end fifo;`
109
110			`architecture altera of fifo is`
111			`component lpm_fifo`
112			`generic (LPM_WIDTH : positive;`
113			`LPM_WIDTHU : positive;`
114			`LPM_NUMWORDS : positive;`
115			`LPM_SHOWAHEAD : string := "OFF";`
116			`LPM_TYPE : string := "LPM_FIFO";`
117			`LPM_HINT : string := "UNUSED");`
118			`port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);`
119			`CLOCK : in std_logic;`
120			`WRREQ : in std_logic;`
121			`RDREQ : in std_logic;`
122			`ACLR : in std_logic;`
123			`SCLR : in std_logic;`
124			`Q : out std_logic_vector(LPM_WIDTH-1 downto 0);`
125			`USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);`
126			`FULL : out std_logic;`
127			`EMPTY : out std_logic);`
128			`end component;`
129			`begin`
130			`altera_fifo: lpm_fifo`
131			`generic map (`
132			`LPM_WIDTH => fifo_width,`
133			`LPM_WIDTHU => used_width,`
134			`LPM_NUMWORDS => fifo_depth,`
135			`LPM_SHOWAHEAD => "OFF",`
136			`LPM_TYPE => "LPM_FIFO",`
137			`LPM_HINT => "UNUSED"`
138			`)`
139			`port map (`
140			`DATA => d_in,`
141			`CLOCK => clk,`
142			`WRREQ => wr,`
143			`RDREQ => rd,`
144			`ACLR => a_clr,`
145			`SCLR => s_clr,`
146			`Q => d_out,`
147			`USEDW => used,`
148			`FULL => full,`
149			`EMPTY => empty`
150			`);`
151			`end altera;`
152
153
154			`library IEEE;`
155			`use IEEE.std_logic_1164.all;`
156
157			`library altera_exemplar;`
158			`use altera_exemplar.all;`
159
160			`entity d_ff is`
161			`port ( d : in STD_LOGIC;`
162			`clk: in STD_LOGIC;`
163			`ena: in STD_LOGIC := '1';`
164			`clr: in STD_LOGIC := '0';`
165			`pre: in STD_LOGIC := '0';`
166			`q : out STD_LOGIC`
167			`);`
168			`end d_ff;`
169
170			`architecture altera of d_ff is`
171			`component dffe`
172			`port ( D : in STD_LOGIC;`
173			`CLK: in STD_LOGIC;`
174			`ENA: in STD_LOGIC;`
175			`CLRN: in STD_LOGIC;`
176			`PRN: in STD_LOGIC;`
177			`Q : out STD_LOGIC);`
178			`end component;`
179			`signal clrn,prn: std_logic;`
180			`begin`
181			`clrn <= not clr;`
182			`prn <= not pre;`
183			`ff: dffe port map (`
184			`D => d,`
185			`CLK => clk,`
186			`ENA => ena,`
187			`CLRN => clrn,`
188			`PRN => prn,`
189			`Q => q`
190			`);`
191			`end altera;`
192
193			`-- Sythetizer library. Contains STD_LOGIC arithmetics`
194

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[/] [wb_vga/] [tags/] [a01/] [technology.vhd] - Blame information for rev 8