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[/] [wb_vga/] [tags/] [a01/] [vga_core.vhd] - Blame information for rev 8

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1 2 tantos 
--
2 
--  File: vga_core.vhd
3 
--
4 
--  (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
5 
--  This code is distributed under the terms and conditions of the GNU General Public Lince.
6 
--
7 
 
8 
library IEEE;
9 
use IEEE.std_logic_1164.all;
10 
 
11 
library work;
12 
--use wb_tk.all;
13 
use work.wb_tk.all;
14 
 
15 
entity vga_core is
16 
        generic (
17 
                -- cannot be overwritten at the moment...
18 
                v_mem_width: positive := 16;
19 
                fifo_size: positive := 256;
20 
                v_addr_width : positive := 20;
21 
                bus_width: positive := 8
22 
        );
23 
        port (
24 
                clk_i: in std_logic;
25 
                clk_en: in std_logic := '1';
26 
                rst_i: in std_logic := '0';
27 
 
28 
                -- CPU bus interface
29 
                dat_i: in std_logic_vector (bus_width-1 downto 0);
30 
                dat_oi: in std_logic_vector (bus_width-1 downto 0);
31 
                dat_o: out std_logic_vector (bus_width-1 downto 0);
32 
                cyc_i: in std_logic;
33 
                ack_o: out std_logic;
34 
                ack_oi: in std_logic;
35 
                we_i: in std_logic;
36 
                vmem_stb_i: in std_logic;
37 
                reg_stb_i: in std_logic;
38 
                adr_i: in std_logic_vector (v_addr_width downto 0);
39 
 
40 
                -- video memory SRAM interface
41 
                s_data : inout std_logic_vector((v_mem_width-1) downto 0);
42 
                s_addr : out std_logic_vector((v_addr_width-1) downto 0);
43 
                s_oen : out std_logic;
44 
                s_wrhn : out std_logic;
45 
                s_wrln : out std_logic;
46 
                s_cen : out std_logic;
47 
 
48 
                -- sync blank and video signal outputs
49 
                h_sync: out std_logic;
50 
                h_blank: out std_logic;
51 
                v_sync: out std_logic;
52 
                v_blank: out std_logic;
53 
                h_tc: out std_logic;
54 
                v_tc: out std_logic;
55 
                blank: out std_logic;
56 
                video_out: out std_logic_vector (7 downto 0);  -- video output binary signal (unused bits are forced to 0)
57 
 
58 
        -- TEST SIGNALS
59 
            T_v_we_o: out std_logic;
60 
            T_v_stb_o: out std_logic;
61 
            T_v_ack_i: out std_logic;
62 
            T_v_adr_o : out std_logic_vector((v_addr_width-1) downto 0);
63 
            T_v_sel_o : out std_logic_vector((v_addr_width/8)-1 downto 0);
64 
            T_v_dat_o : out std_logic_vector((v_mem_width-1) downto 0);
65 
            T_v_dat_i : out std_logic_vector((v_mem_width-1) downto 0)
66 
        );
67 
end vga_core;
68 
 
69 
architecture vga_core of vga_core is
70 
        component video_engine
71 
                generic (
72 
                        v_mem_width: positive := 16;
73 
                        v_addr_width: positive:= 20;
74 
                        fifo_size: positive := 256;
75 
                        dual_scan_fifo_size: positive := 256
76 
                );
77 
                port (
78 
                        clk: in std_logic;
79 
                        clk_en: in std_logic := '1';
80 
                        reset: in std_logic := '0';
81 
 
82 
                        total: in std_logic_vector(v_addr_width-1 downto 0);   -- total video memory size in bytes 7..0
83 
                        fifo_treshold: in std_logic_vector(7 downto 0);        -- priority change threshold
84 
                        bpp: in std_logic_vector(1 downto 0);                  -- number of bits makes up a pixel valid values: 1,2,4,8
85 
                        multi_scan: in std_logic_vector(1 downto 0);           -- number of repeated scans
86 
 
87 
                        hbs: in std_logic_vector(7 downto 0);
88 
                        hss: in std_logic_vector(7 downto 0);
89 
                        hse: in std_logic_vector(7 downto 0);
90 
                        htotal: in std_logic_vector(7 downto 0);
91 
                        vbs: in std_logic_vector(7 downto 0);
92 
                        vss: in std_logic_vector(7 downto 0);
93 
                        vse: in std_logic_vector(7 downto 0);
94 
                        vtotal: in std_logic_vector(7 downto 0);
95 
 
96 
                        pps: in std_logic_vector(7 downto 0);
97 
 
98 
                        high_prior: out std_logic;                      -- signals to the memory arbitrer to give high
99 
                                                                        -- priority to the video engine
100 
                        v_mem_rd: out std_logic;                        -- video memory read request
101 
                        v_mem_rdy: in std_logic;                        -- video memory data ready
102 
                        v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address
103 
                        v_mem_data: in std_logic_vector (v_mem_width-1 downto 0);   -- video memory data
104 
 
105 
                        h_sync: out std_logic;
106 
                        h_blank: out std_logic;
107 
                        v_sync: out std_logic;
108 
                        v_blank: out std_logic;
109 
                        h_tc: out std_logic;
110 
                        v_tc: out std_logic;
111 
                        blank: out std_logic;
112 
                        video_out: out std_logic_vector (7 downto 0)    -- video output binary signal (unused bits are forced to 0)
113 
                );
114 
        end component video_engine;
115 
 
116 
        component wb_async_slave
117 
        generic (
118 
                width: positive := 16;
119 
                addr_width: positive := 20
120 
        );
121 
        port (
122 
                clk_i: in std_logic;
123 
                rst_i: in std_logic := '0';
124 
 
125 
                -- interface for wait-state generator state-machine
126 
                wait_state: in std_logic_vector (3 downto 0);
127 
 
128 
                -- interface to wishbone master device
129 
                adr_i: in std_logic_vector (addr_width-1 downto 0);
130 
                sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
131 
                dat_i: in std_logic_vector (width-1 downto 0);
132 
                dat_o: out std_logic_vector (width-1 downto 0);
133 
                dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
134 
                we_i: in std_logic;
135 
                stb_i: in std_logic;
136 
                ack_o: out std_logic := '0';
137 
                ack_oi: in std_logic := '-';
138 
 
139 
                -- interface to async slave
140 
                a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
141 
                a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
142 
                a_rdn: out std_logic := '1';
143 
                a_wrn: out std_logic := '1';
144 
                a_cen: out std_logic := '1';
145 
                -- byte-enable signals
146 
                a_byen: out std_logic_vector ((addr_width/8)-1 downto 0)
147 
        );
148 
        end component;
149 
 
150 
        component wb_arbiter
151 
        port (
152 
--              clk: in std_logic;
153 
                rst_i: in std_logic := '0';
154 
 
155 
                -- interface to master device a
156 
                a_we_i: in std_logic;
157 
                a_stb_i: in std_logic;
158 
                a_cyc_i: in std_logic;
159 
                a_ack_o: out std_logic;
160 
                a_ack_oi: in std_logic := '-';
161 
                a_err_o: out std_logic;
162 
                a_err_oi: in std_logic := '-';
163 
                a_rty_o: out std_logic;
164 
                a_rty_oi: in std_logic := '-';
165 
 
166 
                -- interface to master device b
167 
                b_we_i: in std_logic;
168 
                b_stb_i: in std_logic;
169 
                b_cyc_i: in std_logic;
170 
                b_ack_o: out std_logic;
171 
                b_ack_oi: in std_logic := '-';
172 
                b_err_o: out std_logic;
173 
                b_err_oi: in std_logic := '-';
174 
                b_rty_o: out std_logic;
175 
                b_rty_oi: in std_logic := '-';
176 
 
177 
                -- interface to shared devices
178 
                s_we_o: out std_logic;
179 
                s_stb_o: out std_logic;
180 
                s_cyc_o: out std_logic;
181 
                s_ack_i: in std_logic;
182 
                s_err_i: in std_logic := '-';
183 
                s_rty_i: in std_logic := '-';
184 
 
185 
                mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
186 
 
187 
                -- misc control lines
188 
                priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
189 
        );
190 
        end component;
191 
 
192 
        component wb_out_reg
193 
        generic (
194 
                width : positive := 8;
195 
                bus_width: positive := 8;
196 
                offset: integer := 0
197 
        );
198 
        port (
199 
                clk_i: in std_logic;
200 
                rst_i: in std_logic;
201 
                rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
202 
 
203 
                dat_i: in std_logic_vector (bus_width-1 downto 0);
204 
                dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
205 
                dat_o: out std_logic_vector (bus_width-1 downto 0);
206 
                q: out std_logic_vector (width-1 downto 0);
207 
                we_i: in std_logic;
208 
                stb_i: in std_logic;
209 
                ack_o: out std_logic;
210 
                ack_oi: in std_logic := '-'
211 
        );
212 
        end component;
213 
 
214 
        component wb_bus_upsize
215 
        generic (
216 
                m_bus_width: positive := 8; -- master bus width
217 
                m_addr_width: positive := 21; -- master bus width
218 
                s_bus_width: positive := 16; -- slave bus width
219 
                little_endien: boolean := true -- if set to false, big endien
220 
        );
221 
        port (
222 
--              clk_i: in std_logic;
223 
--              rst_i: in std_logic := '0';
224 
 
225 
                -- Master bus interface
226 
                m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
227 
                m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
228 
                m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
229 
                m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
230 
                m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
231 
                m_cyc_i: in std_logic;
232 
                m_ack_o: out std_logic;
233 
                m_ack_oi: in std_logic := '-';
234 
                m_err_o: out std_logic;
235 
                m_err_oi: in std_logic := '-';
236 
                m_rty_o: out std_logic;
237 
                m_rty_oi: in std_logic := '-';
238 
                m_we_i: in std_logic;
239 
                m_stb_i: in std_logic;
240 
 
241 
                -- Slave bus interface
242 
                s_adr_o: out std_logic_vector (m_addr_width-2 downto 0);
243 
                s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
244 
                s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
245 
                s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
246 
                s_cyc_o: out std_logic;
247 
                s_ack_i: in std_logic;
248 
                s_err_i: in std_logic := '-';
249 
                s_rty_i: in std_logic := '-';
250 
                s_we_o: out std_logic;
251 
                s_stb_o: out std_logic
252 
        );
253 
        end component;
254 
 
255 
        signal reset_core: std_logic_vector(0 downto 0);
256 
        signal total: std_logic_vector(v_addr_width-1 downto 0);
257 
        signal fifo_treshold: std_logic_vector(7 downto 0);
258 
        signal bpp: std_logic_vector(1 downto 0);
259 
        signal multi_scan: std_logic_vector(1 downto 0);
260 
        signal hbs: std_logic_vector(7 downto 0);
261 
        signal hss: std_logic_vector(7 downto 0);
262 
        signal hse: std_logic_vector(7 downto 0);
263 
        signal htotal: std_logic_vector(7 downto 0);
264 
        signal vbs: std_logic_vector(7 downto 0);
265 
        signal vss: std_logic_vector(7 downto 0);
266 
        signal vse: std_logic_vector(7 downto 0);
267 
        signal vtotal: std_logic_vector(7 downto 0);
268 
        signal pps: std_logic_vector(7 downto 0);
269 
        signal wait_state: std_logic_vector (3 downto 0);
270 
        signal sync_pol: std_logic_vector (3 downto 0);
271 
 
272 
        signal reset_core_do: std_logic_vector(bus_width-1 downto 0);
273 
        signal total0_do: std_logic_vector(bus_width-1 downto 0);
274 
        signal total1_do: std_logic_vector(bus_width-1 downto 0);
275 
        signal total2_do: std_logic_vector(bus_width-1 downto 0);
276 
        signal fifo_treshold_do: std_logic_vector(bus_width-1 downto 0);
277 
        signal bpp_do: std_logic_vector(bus_width-1 downto 0);
278 
        signal multi_scan_do: std_logic_vector(bus_width-1 downto 0);
279 
        signal hbs_do: std_logic_vector(bus_width-1 downto 0);
280 
        signal hss_do: std_logic_vector(bus_width-1 downto 0);
281 
        signal hse_do: std_logic_vector(bus_width-1 downto 0);
282 
        signal htotal_do: std_logic_vector(bus_width-1 downto 0);
283 
        signal vbs_do: std_logic_vector(bus_width-1 downto 0);
284 
        signal vss_do: std_logic_vector(bus_width-1 downto 0);
285 
        signal vse_do: std_logic_vector(bus_width-1 downto 0);
286 
        signal vtotal_do: std_logic_vector(bus_width-1 downto 0);
287 
        signal pps_do: std_logic_vector(bus_width-1 downto 0);
288 
        signal wait_state_do: std_logic_vector(bus_width-1 downto 0);
289 
        signal vm_do: std_logic_vector(bus_width-1 downto 0);
290 
 
291 
        signal reset_core_sel: std_logic;
292 
        signal total0_sel: std_logic;
293 
        signal total1_sel: std_logic;
294 
        signal total2_sel: std_logic;
295 
        signal fifo_treshold_sel: std_logic;
296 
        signal bpp_sel: std_logic;
297 
        signal multi_scan_sel: std_logic;
298 
        signal hbs_sel: std_logic;
299 
        signal hss_sel: std_logic;
300 
        signal hse_sel: std_logic;
301 
        signal htotal_sel: std_logic;
302 
        signal vbs_sel: std_logic;
303 
        signal vss_sel: std_logic;
304 
        signal vse_sel: std_logic;
305 
        signal vtotal_sel: std_logic;
306 
        signal pps_sel: std_logic;
307 
        signal wait_state_sel: std_logic;
308 
        signal sync_pol_sel: std_logic;
309 
 
310 
        signal reset_core_ack: std_logic;
311 
        signal total0_ack: std_logic;
312 
        signal total1_ack: std_logic;
313 
        signal total2_ack: std_logic;
314 
        signal fifo_treshold_ack: std_logic;
315 
        signal bpp_ack: std_logic;
316 
        signal multi_scan_ack: std_logic;
317 
        signal hbs_ack: std_logic;
318 
        signal hss_ack: std_logic;
319 
        signal hse_ack: std_logic;
320 
        signal htotal_ack: std_logic;
321 
        signal vbs_ack: std_logic;
322 
        signal vss_ack: std_logic;
323 
        signal vse_ack: std_logic;
324 
        signal vtotal_ack: std_logic;
325 
        signal pps_ack: std_logic;
326 
        signal wait_state_ack: std_logic;
327 
        signal vm_ack: std_logic;
328 
 
329 
        signal a_adr_o : std_logic_vector((v_addr_width-1) downto 0);
330 
        signal a_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
331 
        signal a_dat_o : std_logic_vector((v_mem_width-1) downto 0);
332 
        signal a_dat_i : std_logic_vector((v_mem_width-1) downto 0);
333 
        signal a_we_o : std_logic;
334 
        signal a_stb_o : std_logic;
335 
        signal a_cyc_o : std_logic;
336 
        signal a_ack_i : std_logic;
337 
 
338 
        signal b_adr_o : std_logic_vector((v_addr_width-1) downto 0);
339 
        signal b_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
340 
--      signal b_dat_o : std_logic_vector((v_mem_width-1) downto 0);
341 
        signal b_dat_i : std_logic_vector((v_mem_width-1) downto 0);
342 
        signal b_stb_o : std_logic;
343 
--      signal b_we_o : std_logic;
344 
--      signal b_cyc_o : std_logic;
345 
        signal b_ack_i : std_logic;
346 
 
347 
        signal v_we_o: std_logic;
348 
        signal v_stb_o: std_logic;
349 
        signal v_ack_i: std_logic;
350 
        signal v_adr_o : std_logic_vector((v_addr_width-1) downto 0);
351 
        signal v_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
352 
        signal v_dat_o : std_logic_vector((v_mem_width-1) downto 0);
353 
        signal v_dat_i : std_logic_vector((v_mem_width-1) downto 0);
354 
 
355 
        signal s_byen : std_logic_vector((v_addr_width/8)-1 downto 0);
356 
 
357 
        signal mux_signal: std_logic;
358 
 
359 
        signal high_prior: std_logic;
360 
 
361 
        signal reset_engine: std_logic;
362 
 
363 
        signal i_h_sync: std_logic;
364 
        signal i_h_blank: std_logic;
365 
        signal i_v_sync: std_logic;
366 
        signal i_v_blank: std_logic;
367 
 
368 
        signal s_wrn : std_logic;
369 
 
370 
begin
371 
        -- map all registers:
372 
        reset_core_reg: wb_out_reg
373 
                generic map( width => 1, bus_width => bus_width , offset => 4 )
374 
                port map(
375 
                stb_i => reset_core_sel,
376 
                q => reset_core,
377 
                rst_val => "1",
378 
                dat_oi => vm_do,
379 
                dat_o => reset_core_do,
380 
                ack_oi => vm_ack,
381 
                ack_o => reset_core_ack,
382 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
383 
        total0_reg: wb_out_reg
384 
                generic map( width => 8, bus_width => bus_width , offset => 0 )
385 
                port map(
386 
                    stb_i => total0_sel,
387 
            q => total(7 downto 0),
388 
            rst_val => "00000000",
389 
            dat_oi => reset_core_do,
390 
            dat_o => total0_do,
391 
            ack_oi => reset_core_ack,
392 
            ack_o => total0_ack,
393 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
394 
        total1_reg: wb_out_reg
395 
                generic map( width => 8, bus_width => bus_width , offset => 0 )
396 
                port map(
397 
            stb_i => total1_sel,
398 
            q => total(15 downto 8),
399 
            rst_val => "00000000",
400 
            dat_oi => total0_do,
401 
            dat_o => total1_do,
402 
            ack_oi => total0_ack,
403 
            ack_o => total1_ack,
404 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
405 
        total2_reg: wb_out_reg
406 
                generic map( width => 4, bus_width => bus_width , offset => 0 )
407 
                port map(
408 
            stb_i => total2_sel,
409 
            q => total(19 downto 16),
410 
            rst_val => "0000",
411 
            dat_oi => total1_do,
412 
            dat_o => total2_do,
413 
            ack_oi => total1_ack,
414 
            ack_o => total2_ack,
415 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
416 
        fifo_treshold_reg: wb_out_reg
417 
                generic map( width => 8, bus_width => bus_width , offset => 0 )
418 
                port map(
419 
            stb_i => fifo_treshold_sel,
420 
            q => fifo_treshold,
421 
            rst_val => "00000000",
422 
            dat_oi => total2_do,
423 
            dat_o => fifo_treshold_do,
424 
            ack_oi => total2_ack,
425 
            ack_o => fifo_treshold_ack,
426 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
427 
        bpp_reg: wb_out_reg
428 
            generic map( width => 2, bus_width => bus_width , offset => 0 )
429 
            port map(
430 
            stb_i => bpp_sel,
431 
            q => bpp,
432 
            rst_val => "00",
433 
            dat_oi => fifo_treshold_do,
434 
            dat_o => bpp_do,
435 
            ack_oi => fifo_treshold_ack,
436 
            ack_o => bpp_ack,
437 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
438 
        multi_scan_reg: wb_out_reg
439 
                generic map( width => 2, bus_width => bus_width , offset => 2 )
440 
                port map(
441 
            stb_i => multi_scan_sel,
442 
            q => multi_scan,
443 
            rst_val => "00",
444 
            dat_oi => bpp_do,
445 
            dat_o => multi_scan_do,
446 
            ack_oi => bpp_ack,
447 
            ack_o => multi_scan_ack,
448 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
449 
        hbs_reg: wb_out_reg
450 
                generic map( width => 8, bus_width => bus_width , offset => 0 )
451 
                port map(
452 
            stb_i => hbs_sel,
453 
            q => hbs,
454 
            rst_val => "00000000",
455 
            dat_oi => multi_scan_do,
456 
            dat_o => hbs_do,
457 
            ack_oi => multi_scan_ack,
458 
            ack_o => hbs_ack,
459 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
460 
        hss_reg: wb_out_reg
461 
                generic map( width => 8, bus_width => bus_width , offset => 0 )
462 
                port map(
463 
            stb_i => hss_sel,
464 
            q => hss,
465 
            rst_val => "00000000",
466 
            dat_oi => hbs_do,
467 
            dat_o => hss_do,
468 
            ack_oi => hbs_ack,
469 
            ack_o => hss_ack,
470 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
471 
        hse_reg: wb_out_reg
472 
                generic map( width => 8, bus_width => bus_width , offset => 0 )
473 
                port map(
474 
            stb_i => hse_sel,
475 
            q => hse,
476 
            rst_val => "00000000",
477 
            dat_oi => hss_do,
478 
            dat_o => hse_do,
479 
            ack_oi => hss_ack,
480 
            ack_o => hse_ack,
481 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
482 
        htotal_reg: wb_out_reg
483 
                generic map( width => 8, bus_width => bus_width , offset => 0 )
484 
                port map(
485 
            stb_i => htotal_sel,
486 
            q => htotal,
487 
            rst_val => "00000000",
488 
            dat_oi => hse_do,
489 
            dat_o => htotal_do,
490 
            ack_oi => hse_ack,
491 
            ack_o => htotal_ack,
492 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
493 
        vbs_reg: wb_out_reg
494 
                generic map( width => 8, bus_width => bus_width , offset => 0 )
495 
                port map(
496 
            stb_i => vbs_sel,
497 
            q => vbs,
498 
            rst_val => "00000000",
499 
            dat_oi => htotal_do,
500 
            dat_o => vbs_do,
501 
            ack_oi => htotal_ack,
502 
            ack_o => vbs_ack,
503 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
504 
        vss_reg: wb_out_reg
505 
                generic map( width => 8, bus_width => bus_width , offset => 0 )
506 
                port map(
507 
            stb_i => vss_sel,
508 
            q => vss,
509 
            rst_val => "00000000",
510 
            dat_oi => vbs_do,
511 
            dat_o => vss_do,
512 
            ack_oi => vbs_ack,
513 
            ack_o => vss_ack,
514 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
515 
        vse_reg: wb_out_reg
516 
                generic map( width => 8, bus_width => bus_width , offset => 0 )
517 
                port map(
518 
            stb_i => vse_sel,
519 
            q => vse,
520 
            rst_val => "00000000",
521 
            dat_oi => vss_do,
522 
            dat_o => vse_do,
523 
            ack_oi => vss_ack,
524 
            ack_o => vse_ack,
525 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
526 
        vtotal_reg: wb_out_reg
527 
                generic map( width => 8, bus_width => bus_width , offset => 0 )
528 
                port map(
529 
            stb_i => vtotal_sel,
530 
            q => vtotal,
531 
            rst_val => "00000000",
532 
            dat_oi => vse_do,
533 
            dat_o => vtotal_do,
534 
            ack_oi => vse_ack,
535 
            ack_o => vtotal_ack,
536 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
537 
        pps_reg: wb_out_reg
538 
                generic map( width => 8, bus_width => bus_width , offset => 0 )
539 
                port map(
540 
            stb_i => pps_sel,
541 
            q => pps,
542 
            rst_val => "00000000",
543 
            dat_oi => vtotal_do,
544 
            dat_o => pps_do,
545 
            ack_oi => vtotal_ack,
546 
            ack_o => pps_ack,
547 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
548 
        wait_state_reg: wb_out_reg
549 
                generic map( width => 4, bus_width => bus_width , offset => 0 )
550 
                port map(
551 
            stb_i => wait_state_sel,
552 
            q => wait_state,
553 
            rst_val => "0000",
554 
            dat_oi => pps_do,
555 
            dat_o => wait_state_do,
556 
            ack_oi => pps_ack,
557 
            ack_o => wait_state_ack,
558 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
559 
        sync_pol_reg: wb_out_reg
560 
                generic map( width => 4, bus_width => bus_width , offset => 4 )
561 
                port map(
562 
            stb_i => sync_pol_sel,
563 
            q => sync_pol,
564 
            rst_val => "0000",
565 
            dat_oi => wait_state_do,
566 
            dat_o => dat_o, -- END OF THE CHAIN
567 
            ack_oi => wait_state_ack,
568 
            ack_o => ack_o, -- END OF THE CHAIN
569 
                we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
570 
 
571 
        reset_engine <= rst_i or reset_core(0);
572 
 
573 
        v_e: video_engine
574 
                generic map ( v_mem_width => v_mem_width, v_addr_width => v_addr_width, fifo_size => fifo_size, dual_scan_fifo_size => fifo_size )
575 
                port map (
576 
                        clk => clk_i,
577 
                        clk_en => clk_en,
578 
                        reset => reset_engine,
579 
                        total => total,
580 
                        fifo_treshold => fifo_treshold,
581 
                        bpp => bpp,
582 
                        multi_scan => multi_scan,
583 
                        hbs => hbs,
584 
                        hss => hss,
585 
                        hse => hse,
586 
                        htotal => htotal,
587 
                        vbs => vbs,
588 
                        vss => vss,
589 
                        vse => vse,
590 
                        vtotal => vtotal,
591 
                        pps => pps,
592 
 
593 
                        high_prior => high_prior,
594 
 
595 
                        v_mem_rd => b_stb_o,
596 
                        v_mem_rdy => b_ack_i,
597 
                        v_mem_addr => b_adr_o,
598 
                        v_mem_data => b_dat_i,
599 
 
600 
                        h_sync => i_h_sync,
601 
                        h_blank => i_h_blank,
602 
                        v_sync => i_v_sync,
603 
                        v_blank => i_v_blank,
604 
                        h_tc => h_tc,
605 
                        v_tc => v_tc,
606 
                        blank => blank,
607 
                        video_out => video_out
608 
                );
609 
 
610 
        h_sync <= i_h_sync xor sync_pol(0);
611 
        v_sync <= i_v_sync xor sync_pol(1);
612 
        h_blank <= i_h_blank;-- xor sync_pol(2);
613 
        v_blank <= i_v_blank;-- xor sync_pol(3);
614 
 
615 
        resize: wb_bus_upsize
616 
                generic map (
617 
                        m_bus_width => bus_width, s_bus_width => v_mem_width, m_addr_width => v_addr_width+1
618 
                )
619 
                port map (
620 
                        m_adr_i => adr_i,
621 
--                      m_sel_i => (others => '1'),
622 
                        m_dat_i => dat_i,
623 
                        m_dat_oi => dat_oi, -- Beginning of the chain
624 
                        m_cyc_i => cyc_i,
625 
                        m_dat_o => vm_do,
626 
                        m_ack_o => vm_ack,
627 
                        m_ack_oi => ack_oi, -- Beginning of the chain
628 
                        m_we_i => we_i,
629 
                        m_stb_i => vmem_stb_i,
630 
 
631 
                        s_adr_o => a_adr_o,
632 
                        s_sel_o => a_sel_o,
633 
                        s_dat_i => a_dat_i,
634 
                        s_dat_o => a_dat_o,
635 
                s_cyc_o => a_cyc_o,
636 
                        s_ack_i => a_ack_i,
637 
                        s_we_o => a_we_o,
638 
                        s_stb_o => a_stb_o
639 
                );
640 
 
641 
 
642 
        arbiter: wb_arbiter
643 
        port map (
644 
                rst_i => reset_engine,
645 
 
646 
                a_we_i => a_we_o,
647 
                a_cyc_i => a_cyc_o,
648 
                a_stb_i => a_stb_o,
649 
                a_ack_o => a_ack_i,
650 
                a_ack_oi => '-',
651 
 
652 
                b_we_i => '0',
653 
                b_cyc_i => b_stb_o,
654 
                b_stb_i => b_stb_o,
655 
                b_ack_o => b_ack_i,
656 
                b_ack_oi => '0', -- maybe not needed at all
657 
 
658 
                s_we_o => v_we_o,
659 
                s_stb_o => v_stb_o,
660 
                s_ack_i => v_ack_i,
661 
 
662 
                mux_signal => mux_signal,
663 
 
664 
                priority => high_prior
665 
        );
666 
 
667 
    b_sel_o <= (others => '1');
668 
 
669 
        bus_mux: process is
670 
        begin
671 
                wait on mux_signal, v_dat_i, a_adr_o, a_dat_o, b_adr_o, a_sel_o, b_sel_o;
672 
                if (mux_signal = '0') then
673 
                        v_adr_o <= a_adr_o;
674 
                        v_sel_o <= a_sel_o;
675 
                        v_dat_o <= a_dat_o;
676 
                        a_dat_i <= v_dat_i;
677 
                        b_dat_i <= (others => '-');
678 
                else
679 
                        v_adr_o <= b_adr_o;
680 
                        v_sel_o <= b_sel_o;
681 
                        v_dat_o <= (others => '-');
682 
                        b_dat_i <= v_dat_i;
683 
                        a_dat_i <= (others => '-');
684 
                end if;
685 
        end process;
686 
 
687 
        mem_driver: wb_async_slave
688 
            generic map (width => v_mem_width, addr_width => v_addr_width)
689 
            port map (
690 
                clk_i => clk_i,
691 
                    rst_i => reset_engine,
692 
 
693 
                wait_state => wait_state,
694 
 
695 
                adr_i => v_adr_o,
696 
                        sel_i => v_sel_o,
697 
                dat_o => v_dat_i,
698 
                dat_i => v_dat_o,
699 
--              dat_oi => (others => '0'), -- may not be needed
700 
                we_i => v_we_o,
701 
                stb_i => v_stb_o,
702 
                ack_o => v_ack_i,
703 
                ack_oi => '0', -- may not be needed
704 
 
705 
                a_data => s_data,
706 
                a_addr => s_addr,
707 
                a_rdn => s_oen,
708 
                a_wrn => s_wrn,
709 
                a_cen => s_cen,
710 
                a_byen => s_byen
711 
            );
712 
 
713 
        s_wrln <= s_wrn or s_byen(0);
714 
        s_wrhn <= s_wrn or s_byen(1);
715 
 
716 
        addr_decoder: process is
717 
        begin
718 
                wait on reg_stb_i, adr_i;
719 
 
720 
                reset_core_sel <= '0';
721 
                total0_sel <= '0';
722 
                total1_sel <= '0';
723 
                total2_sel <= '0';
724 
                fifo_treshold_sel <= '0';
725 
                bpp_sel <= '0';
726 
                multi_scan_sel <= '0';
727 
                hbs_sel <= '0';
728 
                hss_sel <= '0';
729 
                hse_sel <= '0';
730 
                htotal_sel <= '0';
731 
                vbs_sel <= '0';
732 
                vss_sel <= '0';
733 
                vse_sel <= '0';
734 
                vtotal_sel <= '0';
735 
                pps_sel <= '0';
736 
                wait_state_sel <= '0';
737 
                sync_pol_sel <= '0';
738 
 
739 
                if (reg_stb_i = '1') then
740 
                        case (adr_i(4 downto 0)) is
741 
                                when "00000" => total0_sel <= '1';
742 
                                when "00001" => total1_sel <= '1';
743 
                                when "00010" => total2_sel <= '1';
744 
                                when "00011" => fifo_treshold_sel <= '1';
745 
 
746 
                                when "00100" => hbs_sel <= '1';
747 
                                when "00101" => hss_sel <= '1';
748 
                                when "00110" => hse_sel <= '1';
749 
                                when "00111" => htotal_sel <= '1';
750 
 
751 
                                when "01000" => vbs_sel <= '1';
752 
                                when "01001" => vss_sel <= '1';
753 
                                when "01010" => vse_sel <= '1';
754 
                                when "01011" => vtotal_sel <= '1';
755 
 
756 
                                when "01100" => pps_sel <= '1';
757 
                                when "01101" => wait_state_sel <= '1'; sync_pol_sel <= '1';
758 
                                when "01110" => bpp_sel <= '1'; multi_scan_sel <= '1'; reset_core_sel <= '1';
759 
                                when others =>
760 
                        end case;
761 
                end if;
762 
        end process;
763 
 
764 
    -- TEST SIGNALS
765 
    T_v_we_o  <=   v_we_o;
766 
    T_v_stb_o <=   v_stb_o;
767 
    T_v_ack_i <=   v_ack_i;
768 
    T_v_adr_o <=   v_adr_o;
769 
    T_v_sel_o <=   v_sel_o;
770 
    T_v_dat_o <=   v_dat_o;
771 
    T_v_dat_i <=  v_dat_i;
772 
 
773 
end vga_core;
774 
 

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