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[/] [wb_vga/] [trunk/] [accel.vhd] - Blame information for rev 9

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1 4 tantos
--
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--  Address generator and accelerator.
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--
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--  (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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--  This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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-- Standard library.
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library wb_tk;
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use wb_tk.technology.all;
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use wb_tk.all;
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library wb_vga;
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use wb_vga.all;
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entity accel is
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        generic (
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                accel_size: positive := 9;
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                video_addr_width: positive := 20;
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                data_width: positive := 16
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        );
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        port (
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                clk_i: in std_logic;
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                rst_i: in std_logic := '0';
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                -- Slave interface to the CPU side
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                we_i: in std_logic;
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                cyc_i: in std_logic;
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                cur_stb_i: in std_logic;
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                ext_stb_i: in std_logic;
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                acc_stb_i: in std_logic;
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                mem_stb_i: in std_logic;
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        sel_i: in std_logic_vector ((data_width/8)-1 downto 0) := (others => '1');
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                adr_i: in std_logic_vector(accel_size-1 downto 0);
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                dat_i: in std_logic_vector(data_width-1 downto 0);
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                dat_o: out std_logic_vector(data_width-1 downto 0);
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                dat_oi: in std_logic_vector(data_width-1 downto 0);
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                ack_o: out std_logic;
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                ack_oi: in std_logic;
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                -- Master interface to the video memory side.           
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                v_we_o: out std_logic;
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                v_cyc_o: out std_logic;
51 6 tantos
                v_stb_o: out std_logic;
52 4 tantos
 
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                v_adr_o: out std_logic_vector (video_addr_width-1 downto 0);
54 6 tantos
        v_sel_o: out std_logic_vector ((data_width/8)-1 downto 0);
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                v_dat_o: out std_logic_vector (data_width-1 downto 0);
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                v_dat_i: in std_logic_vector (data_width-1 downto 0);
57 4 tantos
 
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                v_ack_i: in std_logic
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        );
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end accel;
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architecture accel of accel is
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        component wb_io_reg
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                generic (
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                        width : positive := video_addr_width;
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                        bus_width: positive := data_width;
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                        offset: integer := 0
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                );
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                port (
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                        clk_i: in std_logic;
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                        rst_i: in std_logic;
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                        rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
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                cyc_i: in std_logic := '1';
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                        stb_i: in std_logic;
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                sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');
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                        we_i: in std_logic;
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                        ack_o: out std_logic;
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                        ack_oi: in std_logic := '-';
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                        adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0');
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                        dat_i: in std_logic_vector (bus_width-1 downto 0);
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                        dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
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                        dat_o: out std_logic_vector (bus_width-1 downto 0);
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                        q: out std_logic_vector (width-1 downto 0);
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                        ext_d: in std_logic_vector (width-1 downto 0) := (others => '-');
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                        ext_we: in std_logic := '0'
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                );
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        end component;
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        component wb_ram
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                generic (
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                        data_width: positive := 8;
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                        addr_width: positive := 10
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                );
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                port (
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                clk_i: in std_logic;
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                        adr_i: in std_logic_vector (addr_width-1 downto 0);
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                        dat_i: in std_logic_vector (data_width-1 downto 0);
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                        dat_oi: in std_logic_vector (data_width-1 downto 0) := (others => '-');
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                        dat_o: out std_logic_vector (data_width-1 downto 0);
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                        cyc_i: in std_logic;
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                        ack_o: out std_logic;
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                        ack_oi: in std_logic := '-';
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                        we_i: in std_logic;
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                        stb_i: in std_logic
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                );
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        end component;
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        signal cursor: std_logic_vector(video_addr_width-1 downto 0);
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        signal accel_ram_d_out: std_logic_vector(video_addr_width-1 downto 0);
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        signal accel_ram_dat_i: std_logic_vector(video_addr_width-1 downto 0);
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        signal accel_ram_stb: std_logic;
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        signal accel_ram_ack: std_logic;
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        signal accel_ram_we: std_logic;
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        signal accel_ram_clk: std_logic;
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        signal next_cur: std_logic_vector(video_addr_width-1 downto 0);
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        signal cur_update: std_logic := '0';
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        signal mem_ack_o: std_logic := '1';
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        signal mem_dat_o: std_logic_vector(data_width-1 downto 0);
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        signal cur_ack_o: std_logic := '1';
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        signal cur_dat_o: std_logic_vector(data_width-1 downto 0);
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        signal ext_value: std_logic_vector(max(video_addr_width - data_width,1)-1 downto 0);
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        signal ext_ext_we: std_logic;
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begin
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        accel_ram_stb <= acc_stb_i or mem_stb_i;
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        accel_ram_we <= we_i and acc_stb_i;
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        accel_ram_clk <= clk_i;
128 6 tantos
        accel_ram_dat_i(min2(video_addr_width-1
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        ,data_width-1) downto 0) <=
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            dat_i(min2(video_addr_width,data_width) - 1 downto 0);
131 4 tantos
        high_accel_dat_gen: if (video_addr_width > data_width) generate
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                accel_ram_dat_i(video_addr_width-1 downto data_width) <= ext_value;
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        end generate;
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        accel_ram: wb_ram
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                generic map (
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                        data_width => video_addr_width,
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                        addr_width => accel_size
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                )
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                port map (
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                        clk_i => clk_i,
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                        cyc_i => cyc_i,
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                        stb_i => accel_ram_stb,
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                        we_i => accel_ram_we,
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                        adr_i => adr_i,
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                        dat_i => accel_ram_dat_i,
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                        dat_o => accel_ram_d_out,
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                        ack_o => accel_ram_ack
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                );
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150 6 tantos
        v_stb_o <= mem_stb_i;
151 4 tantos
        v_cyc_o <= mem_stb_i and cyc_i;
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        v_adr_o <= cursor;
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        v_we_o <= we_i;
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        v_dat_o <= dat_i;
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        next_cur <= cursor + accel_ram_d_out;
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        ext_ext_we <= acc_stb_i and not we_i;
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        ext_reg_gen: if (video_addr_width > data_width) generate
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                ext_reg: wb_io_reg
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                        generic map (
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                                width => video_addr_width - data_width,
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                                bus_width => data_width,
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                                offset => 0
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                        )
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                        port map (
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                                clk_i => clk_i,
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                                rst_i => rst_i,
169 6 tantos
                                rst_val => (video_addr_width - data_width-1 downto 0 => '0'),
170 4 tantos
 
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                        cyc_i => cyc_i,
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                                stb_i => ext_stb_i,
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                        sel_i => sel_i,
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                                we_i => we_i,
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                                ack_o => ack_o,
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                                ack_oi => cur_ack_o,
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                                adr_i => adr_i(size2bits((video_addr_width-1)/data_width)-1 downto 0),
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                                dat_i => dat_i,
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                                dat_oi => cur_dat_o,
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                                dat_o => dat_o,
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                                q => ext_value,
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                                ext_d => accel_ram_d_out(video_addr_width-1 downto data_width),
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                                ext_we => ext_ext_we
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                        );
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        end generate;
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        ext_gen: if (video_addr_width <= data_width) generate
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                dat_o <= cur_dat_o;
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                ack_o <= cur_ack_o;
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                ext_value(0) <= '0';
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        end generate;
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        cur_reg: wb_io_reg
193 6 tantos
                generic map (
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                        width => video_addr_width,
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                        bus_width => data_width,
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                        offset => 0
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                )
198 4 tantos
                port map (
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                        clk_i => clk_i,
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                        rst_i => rst_i,
201 6 tantos
                        rst_val => (video_addr_width-1 downto 0 => '0'),
202 4 tantos
 
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                cyc_i => cyc_i,
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                        stb_i => cur_stb_i,
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                sel_i => sel_i,
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                        we_i => we_i,
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                        ack_o => cur_ack_o,
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                        ack_oi => mem_ack_o,
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                        adr_i => adr_i(size2bits((video_addr_width+data_width-1)/data_width)-1 downto 0),
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                        dat_i => dat_i,
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                        dat_oi => mem_dat_o,
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                        dat_o => cur_dat_o,
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                        q => cursor,
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                        ext_d => next_cur,
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                        ext_we => cur_update
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                );
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218
        cur_update <= mem_stb_i and cyc_i and v_ack_i;
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220 6 tantos
    v_sel_o <= sel_i;
221 4 tantos
        gen_dat_o: for i in dat_o'RANGE generate
222 6 tantos
        gen_dat_o1: if (i < video_addr_width) generate
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                mem_dat_o(i) <= (
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                        (cyc_i and ((accel_ram_d_out(i) and acc_stb_i) or (v_dat_i(i) and mem_stb_i))) or
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                        (dat_oi(i) and ((not (acc_stb_i or mem_stb_i or cur_stb_i)) or (not cyc_i)))
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                );
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        end generate;
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        gen_dat_o2: if (i >= video_addr_width) generate
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                mem_dat_o(i) <= (
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                        (cyc_i and (('0' and acc_stb_i) or (v_dat_i(i) and mem_stb_i))) or
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                        (dat_oi(i) and ((not (acc_stb_i or mem_stb_i or cur_stb_i)) or (not cyc_i)))
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                );
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        end generate;
234 4 tantos
        end generate;
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        mem_ack_o <= (
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                (cyc_i and ((accel_ram_ack and acc_stb_i) or (v_ack_i and mem_stb_i))) or
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                (ack_oi and ((not (acc_stb_i or mem_stb_i or cur_stb_i)) or (not cyc_i)))
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        );
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end accel;

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