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[/] [wb_vga/] [trunk/] [hv_sync.vhd] - Blame information for rev 9

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--
--  Horizontal and vertical sync generator.
--
--  (c) Copyright Andras Tantos <tantos@opencores.org> 2001/03/31
--  This code is distributed under the terms and conditions of the GNU General Public Lince.
--
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity hv_sync is
        port (
                clk: in std_logic;
                pix_clk_en: in std_logic := '1';
                reset: in std_logic := '0';
 
                hbs: in std_logic_vector(7 downto 0);
                hss: in std_logic_vector(7 downto 0);
                hse: in std_logic_vector(7 downto 0);
                htotal: in std_logic_vector(7 downto 0);
                vbs: in std_logic_vector(7 downto 0);
                vss: in std_logic_vector(7 downto 0);
                vse: in std_logic_vector(7 downto 0);
                vtotal: in std_logic_vector(7 downto 0);
 
                h_sync: out std_logic;
                h_blank: out std_logic;
                v_sync: out std_logic;
                v_blank: out std_logic;
                h_tc: out std_logic;
                v_tc: out std_logic;
                blank: out std_logic
        );
end hv_sync;
 
architecture hv_sync of hv_sync is
        component sync_gen
                port (
                        clk: in std_logic;
                        clk_en: in std_logic;
                        reset: in std_logic := '0';
 
                        bs: in std_logic_vector(7 downto 0);
                        ss: in std_logic_vector(7 downto 0);
                        se: in std_logic_vector(7 downto 0);
                        total: in std_logic_vector(7 downto 0);
 
                        sync: out std_logic;
                        blank: out std_logic;
                        tc: out std_logic;
 
                        count: out std_logic_vector (7 downto 0)
                );
        end component;
        signal h_blank_i: std_logic;
        signal v_blank_i: std_logic;
        signal h_tc_i: std_logic;
        signal hcen: std_logic;
        signal vcen: std_logic;
 
        constant h_pre_div_factor: integer := 3;
        constant v_pre_div_factor: integer := 3;
        subtype h_div_var is integer range 0 to h_pre_div_factor;
        subtype v_div_var is integer range 0 to v_pre_div_factor;
 
begin
 
        h_pre_div : process is
                variable cntr: h_div_var;
        begin
                wait until clk'EVENT and clk='1';
                if (reset = '1') then
                        cntr := 0;
                        hcen <= '0';
                else
                        if (pix_clk_en='1') then
                                if (cntr = h_pre_div_factor) then
                                        cntr := 0;
                                        hcen <= '1';
                                else
                                        cntr := cntr+1;
                                        hcen <= '0';
                                end if;
                        else
                                hcen <= '0';
                        end if;
                end if;
        end process;
 
        h_sync_gen : sync_gen
                port map (
                        clk => clk,
                        clk_en => hcen,
                        reset => reset,
 
                        bs => hbs,
                        ss => hss,
                        se => hse,
                        total => htotal,
 
                        sync => h_sync,
                        blank => h_blank_i,
                        tc => h_tc_i
                );
 
        h_tc <= h_tc_i;
 
        v_pre_div : process is
                variable cntr: v_div_var;
        begin
                wait until clk'EVENT and clk='1';
                if (reset = '1') then
                        cntr := 0;
                        vcen <= '0';
                else
                        if (h_tc_i='1') then
                                if (cntr = v_pre_div_factor) then
                                        cntr := 0;
                                        vcen <= '1';
                                else
                                        cntr := cntr+1;
                                        vcen <= '0';
                                end if;
                        else
                                vcen <= '0';
                        end if;
                end if;
        end process;
 
        v_sync_gen : sync_gen
                port map (
                        clk => clk,
                        clk_en => vcen,
                        reset => reset,
 
                        bs => vbs,
                        ss => vss,
                        se => vse,
                        total => vtotal,
 
                        sync => v_sync,
                        blank => v_blank_i,
                        tc => v_tc
                );
 
        blank <= h_blank_i or v_blank_i;
        h_blank <= h_blank_i;
        v_blank <= v_blank_i;
end hv_sync;

Line No.	Rev	Author	Line
1	2	tantos	`--`
2			`-- Horizontal and vertical sync generator.`
3			`--`
4	5	tantos	`-- (c) Copyright Andras Tantos <tantos@opencores.org> 2001/03/31`
5	2	tantos	`-- This code is distributed under the terms and conditions of the GNU General Public Lince.`
6			`--`
7
8			`library IEEE;`
9			`use IEEE.std_logic_1164.all;`
10
11			`entity hv_sync is`
12			`port (`
13			`clk: in std_logic;`
14			`pix_clk_en: in std_logic := '1';`
15			`reset: in std_logic := '0';`
16
17			`hbs: in std_logic_vector(7 downto 0);`
18			`hss: in std_logic_vector(7 downto 0);`
19			`hse: in std_logic_vector(7 downto 0);`
20			`htotal: in std_logic_vector(7 downto 0);`
21			`vbs: in std_logic_vector(7 downto 0);`
22			`vss: in std_logic_vector(7 downto 0);`
23			`vse: in std_logic_vector(7 downto 0);`
24			`vtotal: in std_logic_vector(7 downto 0);`
25
26			`h_sync: out std_logic;`
27			`h_blank: out std_logic;`
28			`v_sync: out std_logic;`
29			`v_blank: out std_logic;`
30			`h_tc: out std_logic;`
31			`v_tc: out std_logic;`
32			`blank: out std_logic`
33			`);`
34			`end hv_sync;`
35
36			`architecture hv_sync of hv_sync is`
37			`component sync_gen`
38			`port (`
39			`clk: in std_logic;`
40			`clk_en: in std_logic;`
41			`reset: in std_logic := '0';`
42
43			`bs: in std_logic_vector(7 downto 0);`
44			`ss: in std_logic_vector(7 downto 0);`
45			`se: in std_logic_vector(7 downto 0);`
46			`total: in std_logic_vector(7 downto 0);`
47
48			`sync: out std_logic;`
49			`blank: out std_logic;`
50			`tc: out std_logic;`
51
52			`count: out std_logic_vector (7 downto 0)`
53			`);`
54			`end component;`
55			`signal h_blank_i: std_logic;`
56			`signal v_blank_i: std_logic;`
57			`signal h_tc_i: std_logic;`
58			`signal hcen: std_logic;`
59			`signal vcen: std_logic;`
60
61			`constant h_pre_div_factor: integer := 3;`
62			`constant v_pre_div_factor: integer := 3;`
63			`subtype h_div_var is integer range 0 to h_pre_div_factor;`
64			`subtype v_div_var is integer range 0 to v_pre_div_factor;`
65
66			`begin`
67
68			`h_pre_div : process is`
69			`variable cntr: h_div_var;`
70			`begin`
71			`wait until clk'EVENT and clk='1';`
72			`if (reset = '1') then`
73			`cntr := 0;`
74			`hcen <= '0';`
75			`else`
76			`if (pix_clk_en='1') then`
77			`if (cntr = h_pre_div_factor) then`
78			`cntr := 0;`
79			`hcen <= '1';`
80			`else`
81			`cntr := cntr+1;`
82			`hcen <= '0';`
83			`end if;`
84			`else`
85			`hcen <= '0';`
86			`end if;`
87			`end if;`
88			`end process;`
89
90			`h_sync_gen : sync_gen`
91			`port map (`
92			`clk => clk,`
93			`clk_en => hcen,`
94			`reset => reset,`
95
96			`bs => hbs,`
97			`ss => hss,`
98			`se => hse,`
99			`total => htotal,`
100
101			`sync => h_sync,`
102			`blank => h_blank_i,`
103			`tc => h_tc_i`
104			`);`
105
106			`h_tc <= h_tc_i;`
107
108			`v_pre_div : process is`
109			`variable cntr: v_div_var;`
110			`begin`
111			`wait until clk'EVENT and clk='1';`
112			`if (reset = '1') then`
113			`cntr := 0;`
114			`vcen <= '0';`
115			`else`
116			`if (h_tc_i='1') then`
117			`if (cntr = v_pre_div_factor) then`
118			`cntr := 0;`
119			`vcen <= '1';`
120			`else`
121			`cntr := cntr+1;`
122			`vcen <= '0';`
123			`end if;`
124			`else`
125			`vcen <= '0';`
126			`end if;`
127			`end if;`
128			`end process;`
129
130			`v_sync_gen : sync_gen`
131			`port map (`
132			`clk => clk,`
133			`clk_en => vcen,`
134			`reset => reset,`
135
136			`bs => vbs,`
137			`ss => vss,`
138			`se => vse,`
139			`total => vtotal,`
140
141			`sync => v_sync,`
142			`blank => v_blank_i,`
143			`tc => v_tc`
144			`);`
145
146			`blank <= h_blank_i or v_blank_i;`
147			`h_blank <= h_blank_i;`
148			`v_blank <= v_blank_i;`
149			`end hv_sync;`

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[/] [wb_vga/] [trunk/] [hv_sync.vhd] - Blame information for rev 9