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[/] [wb_vga/] [trunk/] [video_engine.vhd] - Blame information for rev 9

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--
--  File: video_engine.vhd
--
--  (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
--  This code is distributed under the terms and conditions of the GNU General Public Lince.
--
 
library IEEE;
use IEEE.std_logic_1164.all;
 
library wb_tk;
use wb_tk.technology.all;
 
entity video_engine is
        generic (
                v_mem_width: positive := 16;
                v_addr_width: positive:= 20;
                fifo_size: positive := 256;
                dual_scan_fifo_size: positive := 256
        );
        port (
                clk: in std_logic;
                clk_en: in std_logic := '1';
                reset: in std_logic := '0';
 
                v_mem_end: in std_logic_vector(v_addr_width-1 downto 0);   -- video memory end address in words
                v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words
                fifo_treshold: in std_logic_vector(7 downto 0);        -- priority change threshold
                bpp: in std_logic_vector(1 downto 0);                  -- number of bits makes up a pixel valid values: 1,2,4,8
                multi_scan: in std_logic_vector(1 downto 0);           -- number of repeated scans
 
                hbs: in std_logic_vector(7 downto 0);
                hss: in std_logic_vector(7 downto 0);
                hse: in std_logic_vector(7 downto 0);
                htotal: in std_logic_vector(7 downto 0);
                vbs: in std_logic_vector(7 downto 0);
                vss: in std_logic_vector(7 downto 0);
                vse: in std_logic_vector(7 downto 0);
                vtotal: in std_logic_vector(7 downto 0);
 
                pps: in std_logic_vector(7 downto 0);
 
                high_prior: out std_logic;                      -- signals to the memory arbitrer to give high 
                                                                -- priority to the video engine
                v_mem_rd: out std_logic;                        -- video memory read request
                v_mem_rdy: in std_logic;                        -- video memory data ready
                v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address
                v_mem_data: in std_logic_vector (v_mem_width-1 downto 0);   -- video memory data
 
                h_sync: out std_logic;
                h_blank: out std_logic;
                v_sync: out std_logic;
                v_blank: out std_logic;
                h_tc: out std_logic;
                v_tc: out std_logic;
                blank: out std_logic;
                video_out: out std_logic_vector (7 downto 0)    -- video output binary signal (unused bits are forced to 0)
        );
end video_engine;
 
architecture video_engine of video_engine is
        component hv_sync
                port (
                        clk: in std_logic;
                        pix_clk_en: in std_logic := '1';
                        reset: in std_logic := '0';
 
                        hbs: in std_logic_vector(7 downto 0);
                        hss: in std_logic_vector(7 downto 0);
                        hse: in std_logic_vector(7 downto 0);
                        htotal: in std_logic_vector(7 downto 0);
                        vbs: in std_logic_vector(7 downto 0);
                        vss: in std_logic_vector(7 downto 0);
                        vse: in std_logic_vector(7 downto 0);
                        vtotal: in std_logic_vector(7 downto 0);
 
                        h_sync: out std_logic;
                        h_blank: out std_logic;
                        v_sync: out std_logic;
                        v_blank: out std_logic;
                        h_tc: out std_logic;
                        v_tc: out std_logic;
                        blank: out std_logic
                );
        end component;
 
        component mem_reader
                generic (
                        v_mem_width: positive := 16;
                        v_addr_width: positive:= 20;
                        fifo_size: positive := 256;
                        dual_scan_fifo_size: positive := 256
                );
                port (
                        clk: in std_logic;
                        clk_en: in std_logic;
                        pix_clk_en: in std_logic;
                        reset: in std_logic := '0';
 
                v_mem_end: in std_logic_vector(v_addr_width-1 downto 0);   -- video memory end address in words
                v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words
                        fifo_treshold: in std_logic_vector(7 downto 0);        -- priority change threshold
                        bpp: in std_logic_vector(1 downto 0);                  -- number of bits makes up a pixel valid values: 1,2,4,8
                        multi_scan: in std_logic_vector(1 downto 0);           -- number of repeated scans
 
                        high_prior: out std_logic;                      -- signals to the memory arbitrer to give high 
                                                                        -- priority to the video engine
                        v_mem_rd: out std_logic;                        -- video memory read request
                        v_mem_rdy: in std_logic;                        -- video memory data ready
                        v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address
                        v_mem_data: in std_logic_vector (v_mem_width-1 downto 0);   -- video memory data
 
                        blank: in std_logic;                            -- video sync generator blank output
                        h_tc: in std_logic;                                                     -- horizontal sync pulse. Must be 1 clock wide!
                        video_out: out std_logic_vector (7 downto 0)    -- video output binary signal (unused bits are forced to 0)
                );
        end component;
 
        signal pix_clk_en: std_logic;
 
        signal i_h_sync: std_logic;
        signal i_h_blank: std_logic;
        signal i_v_sync: std_logic;
        signal i_v_blank: std_logic;
        signal i_h_tc: std_logic;
        signal i_v_tc: std_logic;
        signal i_blank: std_logic;
 
begin
        pps_gen: process is
                variable cnt: std_logic_vector(3 downto 0);
        begin
                wait until clk'EVENT and clk = '1';
                if (reset = '1') then
                        cnt := (others => '0');
                        pix_clk_en <= '0';
                else
                        if (clk_en = '0') then
                                pix_clk_en <= '0';
                        else
                                if (cnt = pps(3 downto 0)) then
                                        cnt := (others => '0');
                                        pix_clk_en <= '1';
                                else
                                        cnt := add_one(cnt);
                                        pix_clk_en <= '0';
                                end if;
                        end if;
                end if;
        end process;
 
        mem_engine : mem_reader
                generic map (
                        v_mem_width => v_mem_width,
                        v_addr_width => v_addr_width,
                        fifo_size => fifo_size,
                        dual_scan_fifo_size => dual_scan_fifo_size
                )
                port map (
                        clk => clk,
                        clk_en => clk_en,
                        pix_clk_en => pix_clk_en,
                        reset => reset,
                v_mem_end => v_mem_end,
                    v_mem_start => v_mem_start,
                        fifo_treshold => fifo_treshold,
                        bpp => bpp,
                        multi_scan => multi_scan,
                        high_prior => high_prior,
                        v_mem_rd => v_mem_rd,
                        v_mem_rdy => v_mem_rdy,
                        v_mem_addr => v_mem_addr,
                        v_mem_data => v_mem_data,
                        blank => i_blank,
                        h_tc => i_h_tc,
                        video_out => video_out
                );
 
        sync_engine : hv_sync
                port map (
                        clk => clk,
                        pix_clk_en => pix_clk_en,
                        reset => reset,
 
                        hbs => hbs,
                        hss => hss,
                        hse => hse,
                        htotal => htotal,
                        vbs => vbs,
                        vss => vss,
                        vse => vse,
                        vtotal => vtotal,
 
                        h_sync => i_h_sync,
                        h_blank => i_h_blank,
                        v_sync => i_v_sync,
                        v_blank => i_v_blank,
                        h_tc => i_h_tc,
                        v_tc => i_v_tc,
                        blank => i_blank
                );
 
  -- Delay all sync signals with one pixel. That's becouse of the syncron output of the mem_reader
  sync_delay: process is
  begin
    wait until (clk'EVENT and clk='1');
    if (reset = '1') then
                h_sync <= '0';
                h_blank <= '1';
                v_sync <= '0';
                v_blank <= '1';
        blank <= '1';
    elsif (pix_clk_en = '1') then
                h_sync <= i_h_sync;
                h_blank <= i_h_blank;
                v_sync <= i_v_sync;
                v_blank <= i_v_blank;
        blank <= i_blank;
      end if;
  end process;
 
        h_tc <= i_h_tc;
        v_tc <= i_v_tc;
 
end video_engine;
 

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[/] [wb_vga/] [trunk/] [video_engine.vhd] - Blame information for rev 9

Line No.	Rev	Author	Line
1	2	tantos	`--`
2			`-- File: video_engine.vhd`
3			`--`
4			`-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31`
5			`-- This code is distributed under the terms and conditions of the GNU General Public Lince.`
6			`--`
7
8			`library IEEE;`
9			`use IEEE.std_logic_1164.all;`
10
11	4	tantos	`library wb_tk;`
12			`use wb_tk.technology.all;`
13	2	tantos
14			`entity video_engine is`
15			`generic (`
16			`v_mem_width: positive := 16;`
17			`v_addr_width: positive:= 20;`
18			`fifo_size: positive := 256;`
19			`dual_scan_fifo_size: positive := 256`
20			`);`
21			`port (`
22			`clk: in std_logic;`
23			`clk_en: in std_logic := '1';`
24			`reset: in std_logic := '0';`
25
26	6	tantos	`v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words`
27			`v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words`
28	2	tantos	`fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold`
29			`bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8`
30			`multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans`
31
32			`hbs: in std_logic_vector(7 downto 0);`
33			`hss: in std_logic_vector(7 downto 0);`
34			`hse: in std_logic_vector(7 downto 0);`
35			`htotal: in std_logic_vector(7 downto 0);`
36			`vbs: in std_logic_vector(7 downto 0);`
37			`vss: in std_logic_vector(7 downto 0);`
38			`vse: in std_logic_vector(7 downto 0);`
39			`vtotal: in std_logic_vector(7 downto 0);`
40
41			`pps: in std_logic_vector(7 downto 0);`
42
43			`high_prior: out std_logic; -- signals to the memory arbitrer to give high`
44			`-- priority to the video engine`
45			`v_mem_rd: out std_logic; -- video memory read request`
46			`v_mem_rdy: in std_logic; -- video memory data ready`
47			`v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address`
48			`v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data`
49
50			`h_sync: out std_logic;`
51			`h_blank: out std_logic;`
52			`v_sync: out std_logic;`
53			`v_blank: out std_logic;`
54			`h_tc: out std_logic;`
55			`v_tc: out std_logic;`
56			`blank: out std_logic;`
57			`video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)`
58			`);`
59			`end video_engine;`
60
61			`architecture video_engine of video_engine is`
62			`component hv_sync`
63			`port (`
64			`clk: in std_logic;`
65			`pix_clk_en: in std_logic := '1';`
66			`reset: in std_logic := '0';`
67
68			`hbs: in std_logic_vector(7 downto 0);`
69			`hss: in std_logic_vector(7 downto 0);`
70			`hse: in std_logic_vector(7 downto 0);`
71			`htotal: in std_logic_vector(7 downto 0);`
72			`vbs: in std_logic_vector(7 downto 0);`
73			`vss: in std_logic_vector(7 downto 0);`
74			`vse: in std_logic_vector(7 downto 0);`
75			`vtotal: in std_logic_vector(7 downto 0);`
76
77			`h_sync: out std_logic;`
78			`h_blank: out std_logic;`
79			`v_sync: out std_logic;`
80			`v_blank: out std_logic;`
81			`h_tc: out std_logic;`
82			`v_tc: out std_logic;`
83			`blank: out std_logic`
84			`);`
85			`end component;`
86
87			`component mem_reader`
88			`generic (`
89			`v_mem_width: positive := 16;`
90			`v_addr_width: positive:= 20;`
91			`fifo_size: positive := 256;`
92			`dual_scan_fifo_size: positive := 256`
93			`);`
94			`port (`
95			`clk: in std_logic;`
96			`clk_en: in std_logic;`
97			`pix_clk_en: in std_logic;`
98			`reset: in std_logic := '0';`
99
100	6	tantos	`v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words`
101			`v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words`
102	2	tantos	`fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold`
103			`bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8`
104			`multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans`
105
106			`high_prior: out std_logic; -- signals to the memory arbitrer to give high`
107			`-- priority to the video engine`
108			`v_mem_rd: out std_logic; -- video memory read request`
109			`v_mem_rdy: in std_logic; -- video memory data ready`
110			`v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address`
111			`v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data`
112
113			`blank: in std_logic; -- video sync generator blank output`
114			`h_tc: in std_logic; -- horizontal sync pulse. Must be 1 clock wide!`
115			`video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)`
116			`);`
117			`end component;`
118
119			`signal pix_clk_en: std_logic;`
120
121			`signal i_h_sync: std_logic;`
122			`signal i_h_blank: std_logic;`
123			`signal i_v_sync: std_logic;`
124			`signal i_v_blank: std_logic;`
125			`signal i_h_tc: std_logic;`
126			`signal i_v_tc: std_logic;`
127			`signal i_blank: std_logic;`
128
129			`begin`
130			`pps_gen: process is`
131			`variable cnt: std_logic_vector(3 downto 0);`
132			`begin`
133			`wait until clk'EVENT and clk = '1';`
134			`if (reset = '1') then`
135			`cnt := (others => '0');`
136			`pix_clk_en <= '0';`
137			`else`
138			`if (clk_en = '0') then`
139			`pix_clk_en <= '0';`
140			`else`
141			`if (cnt = pps(3 downto 0)) then`
142			`cnt := (others => '0');`
143			`pix_clk_en <= '1';`
144			`else`
145			`cnt := add_one(cnt);`
146			`pix_clk_en <= '0';`
147			`end if;`
148			`end if;`
149			`end if;`
150			`end process;`
151
152			`mem_engine : mem_reader`
153			`generic map (`
154			`v_mem_width => v_mem_width,`
155			`v_addr_width => v_addr_width,`
156			`fifo_size => fifo_size,`
157			`dual_scan_fifo_size => dual_scan_fifo_size`
158			`)`
159			`port map (`
160			`clk => clk,`
161			`clk_en => clk_en,`
162			`pix_clk_en => pix_clk_en,`
163			`reset => reset,`
164	6	tantos	`v_mem_end => v_mem_end,`
165			`v_mem_start => v_mem_start,`
166	2	tantos	`fifo_treshold => fifo_treshold,`
167			`bpp => bpp,`
168			`multi_scan => multi_scan,`
169			`high_prior => high_prior,`
170			`v_mem_rd => v_mem_rd,`
171			`v_mem_rdy => v_mem_rdy,`
172			`v_mem_addr => v_mem_addr,`
173			`v_mem_data => v_mem_data,`
174			`blank => i_blank,`
175			`h_tc => i_h_tc,`
176			`video_out => video_out`
177			`);`
178
179			`sync_engine : hv_sync`
180			`port map (`
181			`clk => clk,`
182			`pix_clk_en => pix_clk_en,`
183			`reset => reset,`
184
185			`hbs => hbs,`
186			`hss => hss,`
187			`hse => hse,`
188			`htotal => htotal,`
189			`vbs => vbs,`
190			`vss => vss,`
191			`vse => vse,`
192			`vtotal => vtotal,`
193
194			`h_sync => i_h_sync,`
195			`h_blank => i_h_blank,`
196			`v_sync => i_v_sync,`
197			`v_blank => i_v_blank,`
198			`h_tc => i_h_tc,`
199			`v_tc => i_v_tc,`
200			`blank => i_blank`
201			`);`
202
203			`-- Delay all sync signals with one pixel. That's becouse of the syncron output of the mem_reader`
204			`sync_delay: process is`
205			`begin`
206			`wait until (clk'EVENT and clk='1');`
207			`if (reset = '1') then`
208			`h_sync <= '0';`
209			`h_blank <= '1';`
210			`v_sync <= '0';`
211			`v_blank <= '1';`
212			`blank <= '1';`
213			`elsif (pix_clk_en = '1') then`
214			`h_sync <= i_h_sync;`
215			`h_blank <= i_h_blank;`
216			`v_sync <= i_v_sync;`
217			`v_blank <= i_v_blank;`
218			`blank <= i_blank;`
219			`end if;`
220			`end process;`
221
222			`h_tc <= i_h_tc;`
223			`v_tc <= i_v_tc;`
224
225			`end video_engine;`
226