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<link REL="stylesheet" TYPE="text/css" HREF="/people/tantos/styles.css">
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<h1>Wishbone Monitor Controller Palette RAM</h1>
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<h2>Description</h2>
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<strong>Wishbone Monitor Controller Palette RAM</strong> is a small piece of
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dual-ported memory. One of the interfaces is a Wishbone compatible interface
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with the <a href="/cores/wb_tk/wb_extensions.shtml">WishboneTK extensions</a>.
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This interface is write-only. Any read operations attempted on the port would
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result in an error (ERR_O goes active). The other port is an asyncronous
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read-only port. For that port an enable signal is (BLANK) provided. If that signal
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is active all output bits are driven to 0. Otherwise the output will be the data
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stored in the memory location identified by the address provided. This type of
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memory is ideal for palette memory in a monitor controller.
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<h3>Wishbone datasheet</h3>
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<table border>
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<tr><th>Description</th><th>Specification</th></tr>
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<tr><td>General Description </td><td>Monitor controller palette RAM.</td></tr>
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<tr><td>Supported cycles </td><td>Slave read/write<br>Slave block read/write<br>Slave rmw<br></td></tr>
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<tr><td>Data port size </td><td>Configurable</td></tr>
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<tr><td>Data port granularity </td><td>Bus size</td></tr>
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<tr><td>Data port maximum operand size </td><td>Bus size</td></tr>
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<tr><td>Data transfer ordering </td><td>n/a</td></tr>
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<tr><td>Data transfer sequencing </td><td>n/a</td></tr>
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<tr><td>Supported signal list and cross reference to equivalent Wishbone signals</td><td>
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<table>
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<tr><th>Signal name</th><th>Wishbone equiv.</th></tr>
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<tr><td>CLK_I </td><td>CLK_I</td></tr>
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<tr><td>RST_I </td><td>RST_I</td></tr>
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<tr><td>CYC_I </td><td>CYC_I</td></tr>
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<tr><td>STB_I </td><td>STB_I</td></tr>
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<tr><td>WE_I </td><td>WE_I </td></tr>
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<tr><td>ACK_O </td><td>ACK_O</td></tr>
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<tr><td>ERR_O </td><td>ERR_O</td></tr>
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<tr><td>ADR_I(..) </td><td>ADR_I()</td></tr>
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<tr><td>DAT_I(..) </td><td>DAT_I()</td></tr>
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<tr><td>DAT_O(..) </td><td>DAT_O()</td></tr>
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</table>
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</table>
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<h3>Parameter description</h3>
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<table border>
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<tr><td>Parameter name</th><th>Description</th></tr>
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<tr><td>v_dat_width </td><td>True-color pixel output width</td></tr>
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<tr><td>v_adr_width </td><td>Palettized pixel input width</td></tr>
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<tr><td>cpu_dat_width </td><td>CPU data width</td></tr>
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<tr><td>cpu_adr_width </td><td>CPU address width</td></tr>
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</table>
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<h3>Signal description</h3>
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<table border>
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<tr><th>Signal name</th><th>Description</th></tr>
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<tr><th colspan="2">Signals to connect to the pixel memory master</th></tr>
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<tr><td>CYC_I </td><td>Wishbone cycle signal. High value frames blocks of access</td></tr>
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<tr><td>STB_I </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>
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<tr><td>WE_I </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>
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<tr><td>ACK_O </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>
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<tr><td>ACK_OI </td><td>WhisboneTK acknowledge chain input signal</td></tr>
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<tr><td>ERR_O </td><td>Wishbone error signal. High indicates that slave cannot complete the <strong>last cycle in the block</strong>.</td></tr>
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<tr><td>ERR_OI </td><td>WhisboneTK error chain input signal</td></tr>
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<tr><td>ADR_I(cpu_adr_width-1..0) </td><td>Wishbone address bus signals</td></tr>
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<tr><td>DAT_I(cpu_dat_width-1..0) </td><td>Wishbone data bus input (to slave direction) signals</td></tr>
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<tr><td>DAT_O(cpu_dat_width-1..0) </td><td>Wishbone data bus output (to master direction) signals</td></tr>
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<tr><td>DAT_OI(cpu_dat_width-1..0) </td><td>WhisboneTK data bus chain input signal</td></tr>
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<tr><th colspan="2">Non Wishbone signals</th></tr>
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<tr><td>BLANK </td><td>Blanking input signal. If active (high) output is forced to all 0s</td></tr>
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<tr><td>V_DAT_I(v_adr_width-1 DOWNTO 0)</td><td>Palettized data input</td></tr>
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<tr><td>V_DAT_O(v_dat_width-1 DOWNTO 0)</td><td>True-color data output</td></tr>
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</table>
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<h2>Author & Maintainer</h2>
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<p>
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<a href="/people/tantos">Andras Tantos</a>
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