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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: ddrsdram_tb.cpp
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//
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// Project: A wishbone controlled DDR3 SDRAM memory controller.
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//
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// Purpose: To determine whether or not the wbddrsdram Verilog module works.
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// Run this program with no arguments. If the last line output
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// is "SUCCESS", you will know it works.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <stdio.h>
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#include "verilated.h"
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#include "Vwbddrsdram.h"
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#include "ddrsdramsim.h"
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const int BOMBCOUNT = 2048,
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SDRAMMASK = 0x3ffffff,
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LGMEMSIZE = 28;
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class DDRSDRAM_TB {
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long m_tickcount;
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Vwbddrsdram *m_core;
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DDRSDRAMSIM *m_sdram;
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bool m_bomb;
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public:
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DDRSDRAM_TB(void) {
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m_core = new Vwbddrsdram;
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m_sdram= new DDRSDRAMSIM(LGMEMSIZE);
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}
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unsigned &operator[](const int index) { return (*m_sdram)[index]; }
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void set(unsigned addr, unsigned v) {
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(*m_sdram)[addr] = v;
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}
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void tick(void) {
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m_core->i_clk = 1;
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m_core->i_ddr_data = (*m_sdram)(
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m_core->o_ddr_reset_n,
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m_core->o_ddr_cke,
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m_core->o_ddr_cs_n,
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m_core->o_ddr_ras_n,
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m_core->o_ddr_cas_n,
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m_core->o_ddr_we_n,
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m_core->o_ddr_dqs,
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m_core->o_ddr_dm,
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m_core->o_ddr_odt,
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m_core->o_ddr_bus_oe,
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m_core->o_ddr_addr,
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m_core->o_ddr_ba,
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m_core->o_ddr_data);
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printf("%08lx-WB: %s/%s %s%s%s %s@0x%08x[%08x/%08x] -- ",
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m_tickcount,
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(m_core->i_wb_cyc)?"CYC":" ",
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(m_core->i_wb_stb)?"STB":" ",
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(m_core->o_wb_stall)?"STALL":" ",
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(m_core->o_wb_ack)?"ACK":" ",
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(m_core->o_cmd_accepted)?"BUS":" ",
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(m_core->i_wb_we)?"W":"R",
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(m_core->i_wb_addr),
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(m_core->i_wb_data),
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(m_core->o_wb_data));
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printf("%s%s %d%d%d%d %s%s%s%s B[%d]@%04x %08x %08x",
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(m_core->o_ddr_reset_n)?" ":"R",
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(m_core->o_ddr_cke)?"CK":" ",
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(m_core->o_ddr_cs_n),
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(m_core->o_ddr_ras_n),
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(m_core->o_ddr_cas_n),
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(m_core->o_ddr_we_n),
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//
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(m_core->o_ddr_dqs)?"D":" ",
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(m_core->o_ddr_dm)?"M":" ",
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(m_core->o_ddr_odt)?"O":" ",
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(m_core->o_ddr_bus_oe)?"E":" ",
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//
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(m_core->o_ddr_ba),
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(m_core->o_ddr_addr),
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(m_core->i_ddr_data),
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(m_core->o_ddr_data));
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// Reset logic
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printf(" RST(%06x%s[%d] - %08x->%08x)",
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m_core->v__DOT__reset_timer,
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(m_core->v__DOT__reset_ztimer)?"Z":" ",
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(m_core->v__DOT__reset_address),
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(m_core->v__DOT__reset_instruction),
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(m_core->v__DOT__reset_cmd));
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extern int gbl_state, gbl_counts;
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printf(" %d:%08x ", gbl_state, gbl_counts);
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if (m_core->v__DOT__reset_override)
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printf(" OVERRIDE");
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printf("\n");
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m_core->eval();
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m_core->i_clk = 0;
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m_core->eval();
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m_tickcount++;
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/*
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if ((m_core->o_wb_ack)&&(!m_core->i_wb_cyc)) {
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printf("SETTING ERR TO TRUE!!!!! ACK w/ no CYC\n");
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// m_bomb = true;
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}
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*/
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}
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void reset(void) {
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m_core->i_reset = 1;
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m_core->i_wb_cyc = 0;
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m_core->i_wb_stb = 0;
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tick();
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m_core->i_reset = 0;
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}
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void wb_tick(void) {
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m_core->i_wb_cyc = 0;
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m_core->i_wb_stb = 0;
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tick();
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}
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unsigned wb_read(unsigned a) {
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int errcount = 0;
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unsigned result;
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printf("WB-READ(%08x)\n", a);
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m_core->i_wb_cyc = 1;
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m_core->i_wb_stb = 1;
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m_core->i_wb_we = 0;
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m_core->i_wb_addr= a & SDRAMMASK;
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if (m_core->o_wb_stall) {
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while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))
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tick();
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} else
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tick();
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m_core->i_wb_stb = 0;
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while((errcount++ < BOMBCOUNT)&&(!m_core->o_wb_ack))
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tick();
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result = m_core->o_wb_data;
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// Release the bus?
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m_core->i_wb_cyc = 0;
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m_core->i_wb_stb = 0;
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if(errcount >= BOMBCOUNT) {
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printf("SETTING ERR TO TRUE!!!!!\n");
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m_bomb = true;
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} else if (!m_core->o_wb_ack) {
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printf("SETTING ERR TO TRUE--NO ACK, NO TIMEOUT\n");
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m_bomb = true;
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}
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tick();
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return result;
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}
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void wb_read(unsigned a, int len, unsigned *buf) {
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int errcount = 0;
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int THISBOMBCOUNT = BOMBCOUNT * len;
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int cnt, rdidx, inc;
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printf("WB-READ(%08x, %d)\n", a, len);
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while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))
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wb_tick();
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if (errcount >= BOMBCOUNT) {
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m_bomb = true;
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return;
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}
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errcount = 0;
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m_core->i_wb_cyc = 1;
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m_core->i_wb_stb = 1;
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m_core->i_wb_we = 0;
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m_core->i_wb_addr= a & SDRAMMASK;
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rdidx =0; cnt = 0;
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inc = 1;
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do {
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int s;
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s = (m_core->o_wb_stall==0)?0:1;
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tick();
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if (!s)
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m_core->i_wb_addr += inc;
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cnt += (s==0)?1:0;
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if (m_core->o_wb_ack)
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buf[rdidx++] = m_core->o_wb_data;
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} while((cnt < len)&&(errcount++ < THISBOMBCOUNT));
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m_core->i_wb_stb = 0;
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while((rdidx < len)&&(errcount++ < THISBOMBCOUNT)) {
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tick();
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if (m_core->o_wb_ack)
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buf[rdidx++] = m_core->o_wb_data;
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}
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// Release the bus?
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m_core->i_wb_cyc = 0;
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if(errcount >= THISBOMBCOUNT) {
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printf("SETTING ERR TO TRUE!!!!! (errcount=%08x, THISBOMBCOUNT=%08x)\n", errcount, THISBOMBCOUNT);
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m_bomb = true;
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} else if (!m_core->o_wb_ack) {
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printf("SETTING ERR TO TRUE--NO ACK, NO TIMEOUT\n");
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m_bomb = true;
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}
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tick();
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}
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void wb_write(unsigned a, unsigned int v) {
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int errcount = 0;
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printf("WB-WRITE(%08x) = %08x\n", a, v);
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m_core->i_wb_cyc = 1;
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m_core->i_wb_stb = 1;
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m_core->i_wb_we = 1;
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m_core->i_wb_addr= a & SDRAMMASK;
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m_core->i_wb_data= v;
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if (m_core->o_wb_stall)
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while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))
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tick();
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tick();
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m_core->i_wb_stb = 0;
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while((errcount++ < BOMBCOUNT)&&(!m_core->o_wb_ack))
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tick();
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// Release the bus?
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m_core->i_wb_cyc = 0;
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m_core->i_wb_stb = 0;
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if(errcount >= BOMBCOUNT) {
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printf("SETTING ERR TO TRUE!!!!!\n");
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m_bomb = true;
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} tick();
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}
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void wb_write(unsigned a, unsigned int ln, unsigned int *buf) {
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unsigned errcount = 0, nacks = 0;
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m_core->i_wb_cyc = 1;
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m_core->i_wb_stb = 1;
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for(unsigned stbcnt=0; stbcnt<ln; stbcnt++) {
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m_core->i_wb_we = 1;
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m_core->i_wb_addr= (a+stbcnt) & SDRAMMASK;
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m_core->i_wb_data= buf[stbcnt];
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errcount = 0;
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while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall)) {
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tick(); if (m_core->o_wb_ack) nacks++;
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}
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// Tick, now that we're not stalled. This is the tick
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// that gets accepted.
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tick(); if (m_core->o_wb_ack) nacks++;
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}
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m_core->i_wb_stb = 0;
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errcount = 0;
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while((nacks < ln)&&(errcount++ < BOMBCOUNT)) {
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tick();
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if (m_core->o_wb_ack) {
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nacks++;
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errcount = 0;
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}
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}
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// Release the bus
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m_core->i_wb_cyc = 0;
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m_core->i_wb_stb = 0;
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if(errcount >= BOMBCOUNT) {
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printf("SETTING ERR TO TRUE!!!!!\n");
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m_bomb = true;
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} tick();
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}
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bool bombed(void) const { return m_bomb; }
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};
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| 329 |
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| 330 |
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void uload(unsigned len, unsigned *buf) {
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| 331 |
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FILE *fp = fopen("/dev/urandom", "r");
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| 332 |
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| 333 |
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if ((NULL == fp)||(len != fread(buf, sizeof(unsigned), len, fp))) {
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| 334 |
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for(int i=0; i<(int)len; i++)
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buf[i] = rand();
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| 336 |
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} if (NULL == fp)
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| 337 |
|
|
fclose(fp);
|
| 338 |
|
|
}
|
| 339 |
|
|
|
| 340 |
|
|
int main(int argc, char **argv) {
|
| 341 |
|
|
Verilated::commandArgs(argc, argv);
|
| 342 |
|
|
DDRSDRAM_TB *tb = new DDRSDRAM_TB;
|
| 343 |
|
|
unsigned *rdbuf, *mbuf;
|
| 344 |
|
|
int nw = 3, nr = 13;
|
| 345 |
|
|
unsigned mlen = (1<<(LGMEMSIZE-2));
|
| 346 |
|
|
|
| 347 |
|
|
printf("Giving the core 140k cycles to start up\n");
|
| 348 |
|
|
// Before testing, let's give the unit time enough to warm up
|
| 349 |
|
|
tb->reset();
|
| 350 |
|
|
for(int i=0; i<140850; i++)
|
| 351 |
|
|
tb->wb_tick();
|
| 352 |
|
|
|
| 353 |
|
|
printf("Getting some memory ...\n");
|
| 354 |
|
|
rdbuf = new unsigned[mlen];
|
| 355 |
|
|
mbuf = new unsigned[mlen]; // Match buffer
|
| 356 |
|
|
printf("Charging my memory with random values\n");
|
| 357 |
|
|
uload(mlen, rdbuf);
|
| 358 |
|
|
|
| 359 |
|
|
// First test: singular reads through the memory, followed by
|
| 360 |
|
|
// singular writes
|
| 361 |
|
|
printf("Starting the single-read test\n");
|
| 362 |
|
|
for(int i=0; i<(int)mlen; i++) {
|
| 363 |
|
|
tb->wb_write(i, rdbuf[i]);
|
| 364 |
|
|
tb->wb_tick();
|
| 365 |
|
|
if ((*tb)[i] != rdbuf[i]) {
|
| 366 |
|
|
printf("WRITE[%06x] = %08x (Expecting %08x) FAILED\n",
|
| 367 |
|
|
i, (*tb)[i], rdbuf[i]);
|
| 368 |
|
|
goto test_failure;
|
| 369 |
|
|
} if (tb->bombed())
|
| 370 |
|
|
goto test_failure;
|
| 371 |
|
|
|
| 372 |
|
|
} for(int i=0; i<(int)mlen; i++) {
|
| 373 |
|
|
unsigned v;
|
| 374 |
|
|
if (rdbuf[i] != (v=tb->wb_read(i))) {
|
| 375 |
|
|
printf("READ[%06x] = %08x (Expecting %08x)\n",
|
| 376 |
|
|
i, v, rdbuf[i]);
|
| 377 |
|
|
goto test_failure;
|
| 378 |
|
|
} if (tb->bombed())
|
| 379 |
|
|
goto test_failure;
|
| 380 |
|
|
tb->wb_tick();
|
| 381 |
|
|
}
|
| 382 |
|
|
|
| 383 |
|
|
// Second test: Vector writes going through all memory, followed a
|
| 384 |
|
|
// massive vector read
|
| 385 |
|
|
uload(mlen, rdbuf); // Get some new values
|
| 386 |
|
|
tb->wb_write(0, mlen, rdbuf);
|
| 387 |
|
|
if (tb->bombed())
|
| 388 |
|
|
goto test_failure;
|
| 389 |
|
|
for(int i=0; i<(int)mlen; i++) {
|
| 390 |
|
|
unsigned v;
|
| 391 |
|
|
if (rdbuf[i] != (v=(*tb)[i])) {
|
| 392 |
|
|
printf("V-WRITE[%06x] = %08x (Expecting %08x)\n",
|
| 393 |
|
|
i, v, rdbuf[i]);
|
| 394 |
|
|
goto test_failure;
|
| 395 |
|
|
}
|
| 396 |
|
|
}
|
| 397 |
|
|
|
| 398 |
|
|
tb->wb_read( 0, mlen, mbuf);
|
| 399 |
|
|
if (tb->bombed())
|
| 400 |
|
|
goto test_failure;
|
| 401 |
|
|
for(int i=0; i<(int)mlen; i++) {
|
| 402 |
|
|
if (rdbuf[i] != mbuf[i]) {
|
| 403 |
|
|
printf("V-READ[%06x] = %08x (Expecting %08x)\n",
|
| 404 |
|
|
i, mbuf[i], rdbuf[i]);
|
| 405 |
|
|
goto test_failure;
|
| 406 |
|
|
}
|
| 407 |
|
|
}
|
| 408 |
|
|
|
| 409 |
|
|
// Third test: Vector writes going through all memory, an prime number
|
| 410 |
|
|
// of values at a time, followed by reads via a different prime number
|
| 411 |
|
|
for(int i=0; i<(int)mlen; i+=nw) {
|
| 412 |
|
|
int ln = ((int)mlen-i>nw)?nw:mlen-i;
|
| 413 |
|
|
tb->wb_write(i, nw, &rdbuf[i]);
|
| 414 |
|
|
for(int j=0; j<ln; j++) {
|
| 415 |
|
|
if ((*tb)[i+j] != rdbuf[i+j]) {
|
| 416 |
|
|
printf("P-WRITE[%06x] = %08x (Expecting %08x) FAILED\n",
|
| 417 |
|
|
i, (*tb)[i], rdbuf[i]);
|
| 418 |
|
|
goto test_failure;
|
| 419 |
|
|
}
|
| 420 |
|
|
} if (tb->bombed())
|
| 421 |
|
|
goto test_failure;
|
| 422 |
|
|
} for(int i=0; i<(int)mlen; i+=nr) {
|
| 423 |
|
|
int ln = ((int)mlen-i>nr)?nr:mlen-i;
|
| 424 |
|
|
tb->wb_write(i, nr, &mbuf[i]);
|
| 425 |
|
|
for(int j=0; j<ln; j++) {
|
| 426 |
|
|
if (mbuf[i+j] != rdbuf[i+j]) {
|
| 427 |
|
|
printf("P-READ[%06x] = %08x (Expecting %08x) FAILED\n",
|
| 428 |
|
|
i, mbuf[i], rdbuf[i]);
|
| 429 |
|
|
goto test_failure;
|
| 430 |
|
|
}
|
| 431 |
|
|
} if (tb->bombed())
|
| 432 |
|
|
goto test_failure;
|
| 433 |
|
|
}
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
printf("SUCCESS!!\n");
|
| 437 |
|
|
exit(0);
|
| 438 |
|
|
test_failure:
|
| 439 |
|
|
printf("FAIL-HERE\n");
|
| 440 |
|
|
for(int i=0; i<64; i++)
|
| 441 |
|
|
tb->tick();
|
| 442 |
|
|
printf("TEST FAILED\n");
|
| 443 |
|
|
exit(-1);
|
| 444 |
|
|
}
|
