1 |
21 |
dgisselq |
///////////////////////////////////////////////////////////////////////////////
|
2 |
2 |
dgisselq |
//
|
3 |
|
|
// Filename: wbddrsdram.v
|
4 |
|
|
//
|
5 |
21 |
dgisselq |
// Project: ZipVersa, Versa Brd implementation using ZipCPU infrastructure
|
6 |
2 |
dgisselq |
//
|
7 |
16 |
dgisselq |
// Purpose: To control a DDR3-1333 (9-9-9) memory from a wishbone bus.
|
8 |
|
|
// In our particular implementation, there will be two command
|
9 |
|
|
// clocks (2.5 ns) per FPGA clock (i_clk) at 5 ns, and 64-bits transferred
|
10 |
|
|
// per FPGA clock. However, since the memory is focused around 128-bit
|
11 |
|
|
// word transfers, attempts to transfer other than adjacent 64-bit words
|
12 |
|
|
// will (of necessity) suffer stalls. Please see the documentation for
|
13 |
|
|
// more details of how this controller works.
|
14 |
2 |
dgisselq |
//
|
15 |
|
|
// Creator: Dan Gisselquist, Ph.D.
|
16 |
|
|
// Gisselquist Technology, LLC
|
17 |
|
|
//
|
18 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
19 |
|
|
//
|
20 |
21 |
dgisselq |
// Copyright (C) 2019, Gisselquist Technology, LLC
|
21 |
2 |
dgisselq |
//
|
22 |
|
|
// This program is free software (firmware): you can redistribute it and/or
|
23 |
21 |
dgisselq |
// modify it under the terms of the GNU General Public License as published
|
24 |
2 |
dgisselq |
// by the Free Software Foundation, either version 3 of the License, or (at
|
25 |
|
|
// your option) any later version.
|
26 |
|
|
//
|
27 |
|
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
28 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
29 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
30 |
|
|
// for more details.
|
31 |
|
|
//
|
32 |
|
|
// You should have received a copy of the GNU General Public License along
|
33 |
21 |
dgisselq |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
|
34 |
2 |
dgisselq |
// target there if the PDF file isn't present.) If not, see
|
35 |
|
|
// <http://www.gnu.org/licenses/> for a copy.
|
36 |
|
|
//
|
37 |
|
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
38 |
|
|
// http://www.gnu.org/licenses/gpl.html
|
39 |
|
|
//
|
40 |
|
|
//
|
41 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
42 |
|
|
//
|
43 |
|
|
//
|
44 |
21 |
dgisselq |
`default_nettype none
|
45 |
2 |
dgisselq |
//
|
46 |
3 |
dgisselq |
module wbddrsdram(i_clk, i_reset,
|
47 |
16 |
dgisselq |
// Wishbone inputs
|
48 |
2 |
dgisselq |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
|
49 |
16 |
dgisselq |
i_wb_sel,
|
50 |
|
|
// Wishbone outputs
|
51 |
|
|
o_wb_ack, o_wb_stall, o_wb_data,
|
52 |
17 |
dgisselq |
// Memory command wires
|
53 |
21 |
dgisselq |
o_ddr_reset_n, o_ddr_cke, // o_ddr_bus_oe,
|
54 |
18 |
dgisselq |
o_ddr_cmd_a, o_ddr_cmd_b, o_ddr_cmd_c, o_ddr_cmd_d,
|
55 |
17 |
dgisselq |
// And the data wires to go with them ....
|
56 |
21 |
dgisselq |
o_ddr_data, i_ddr_data);
|
57 |
16 |
dgisselq |
// These parameters are not really meant for adjusting from the
|
58 |
|
|
// top level. These are more internal variables, recorded here
|
59 |
|
|
// so that things can be automatically adjusted without much
|
60 |
|
|
// problem.
|
61 |
18 |
dgisselq |
parameter CKRP = 0;
|
62 |
|
|
parameter BUSNOW = 2, BUSREG = BUSNOW-1;
|
63 |
21 |
dgisselq |
localparam AW = 24;
|
64 |
|
|
localparam CMDW = 28;
|
65 |
|
|
localparam LANES = 2;
|
66 |
|
|
localparam DW = LANES * 8 * 8;
|
67 |
|
|
localparam DDRDW = LANES * 8 * 8; // 8b per lane, 2 side ea of 4cyc
|
68 |
|
|
//
|
69 |
|
|
// Possible commands to the DDR3 memory. These consist of settings
|
70 |
|
|
// for the bits: o_wb_cs_n, o_wb_ras_n, o_wb_cas_n, and o_wb_we_n,
|
71 |
|
|
// respectively.
|
72 |
|
|
localparam [3:0] DDR_MRSET = 4'b0000;
|
73 |
|
|
localparam [3:0] DDR_REFRESH = 4'b0001;
|
74 |
|
|
localparam [3:0] DDR_PRECHARGE = 4'b0010;
|
75 |
|
|
localparam [3:0] DDR_ACTIVATE = 4'b0011;
|
76 |
|
|
localparam [3:0] DDR_WRITE = 4'b0100;
|
77 |
|
|
localparam [3:0] DDR_READ = 4'b0101;
|
78 |
|
|
localparam [3:0] DDR_ZQS = 4'b0110;
|
79 |
|
|
localparam [3:0] DDR_NOOP = 4'b0111;
|
80 |
|
|
// localparam [3:0] DDR_DESELECT = 4'b1???;
|
81 |
|
|
//
|
82 |
|
|
// In this controller, 24-bit commands tend to be passed around. These
|
83 |
|
|
// 'commands' are bit fields. Here we specify the bits associated with
|
84 |
|
|
// the bit fields.
|
85 |
|
|
localparam DDR_RSTDONE = 24;// End the reset sequence?
|
86 |
|
|
localparam DDR_RSTTIMER = 23;// Does this reset command take multiple clocks?
|
87 |
|
|
localparam DDR_RSTBIT = 22;// Value to place on reset_n
|
88 |
|
|
localparam DDR_CKEBIT = 21;// Should this reset command set CKE?
|
89 |
|
|
//
|
90 |
|
|
// Refresh command bit fields
|
91 |
|
|
localparam DDR_PREREFRESH_STALL = 24;
|
92 |
|
|
localparam DDR_NEEDREFRESH = 23;
|
93 |
|
|
localparam DDR_RFTIMER = 22;
|
94 |
|
|
localparam DDR_RFBEGIN = 21;
|
95 |
|
|
//
|
96 |
|
|
localparam DDR_CMDLEN = 21;
|
97 |
|
|
localparam DDR_CSBIT = 20;
|
98 |
|
|
localparam DDR_RASBIT = 19;
|
99 |
|
|
localparam DDR_CASBIT = 18;
|
100 |
|
|
localparam DDR_WEBIT = 17;
|
101 |
|
|
localparam DDR_NOPTIMER = 16; // Steal this from BA bits
|
102 |
|
|
localparam DDR_BABITS = 3; // BABITS are really from 18:16, they are 3 bits
|
103 |
|
|
localparam DDR_ADDR_BITS = 14;
|
104 |
|
|
//
|
105 |
|
|
localparam LGNROWS = 14,
|
106 |
|
|
LGNBANKS= 3;
|
107 |
|
|
localparam LGFIFOLN = 3;
|
108 |
|
|
localparam FIFOLEN = 8;
|
109 |
|
|
|
110 |
|
|
//
|
111 |
16 |
dgisselq |
// The commands (above) include (in this order):
|
112 |
|
|
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
113 |
|
|
// o_ddr_dqs, o_ddr_dm, o_ddr_odt
|
114 |
21 |
dgisselq |
input wire i_clk, // *MUST* be at 200 MHz for this to work
|
115 |
16 |
dgisselq |
i_reset;
|
116 |
2 |
dgisselq |
// Wishbone inputs
|
117 |
21 |
dgisselq |
input wire i_wb_cyc, i_wb_stb, i_wb_we;
|
118 |
18 |
dgisselq |
// The bus address needs to identify a single 128-bit word of interest
|
119 |
21 |
dgisselq |
input wire [AW-1:0] i_wb_addr;
|
120 |
|
|
input wire [DW-1:0] i_wb_data;
|
121 |
|
|
input wire [DW/8-1:0] i_wb_sel;
|
122 |
16 |
dgisselq |
// Wishbone responses/outputs
|
123 |
21 |
dgisselq |
output reg o_wb_ack, o_wb_stall;
|
124 |
|
|
output reg [DW-1:0] o_wb_data;
|
125 |
16 |
dgisselq |
// DDR memory command wires
|
126 |
18 |
dgisselq |
output reg o_ddr_reset_n, o_ddr_cke;
|
127 |
16 |
dgisselq |
// CMDs are:
|
128 |
|
|
// 4 bits of CS, RAS, CAS, WE
|
129 |
|
|
// 3 bits of bank
|
130 |
|
|
// 14 bits of Address
|
131 |
|
|
// 1 bit of DQS (strobe active, or not)
|
132 |
|
|
// 4 bits of mask (one per byte)
|
133 |
|
|
// 1 bit of ODT
|
134 |
|
|
// ----
|
135 |
|
|
// 27 bits total
|
136 |
21 |
dgisselq |
output wire [CMDW-1:0] o_ddr_cmd_a, o_ddr_cmd_b,
|
137 |
|
|
o_ddr_cmd_c, o_ddr_cmd_d;
|
138 |
|
|
output reg [DDRDW-1:0] o_ddr_data;
|
139 |
|
|
input wire [DDRDW-1:0] i_ddr_data;
|
140 |
2 |
dgisselq |
|
141 |
21 |
dgisselq |
integer ik, jk;
|
142 |
3 |
dgisselq |
|
143 |
21 |
dgisselq |
////////
|
144 |
|
|
//
|
145 |
|
|
(* keep *) reg reset_override, reset_ztimer,
|
146 |
|
|
maintenance_override;
|
147 |
18 |
dgisselq |
|
148 |
21 |
dgisselq |
////////
|
149 |
|
|
//
|
150 |
|
|
reg [3:0] reset_address;
|
151 |
|
|
reg [DDR_CMDLEN-1:0] reset_cmd, cmd_a, cmd_b, cmd_c, cmd_d,
|
152 |
18 |
dgisselq |
refresh_cmd, maintenance_cmd;
|
153 |
21 |
dgisselq |
reg [24:0] reset_instruction;
|
154 |
|
|
reg [16:0] reset_timer;
|
155 |
|
|
|
156 |
|
|
wire [16:0] w_ckXPR, w_ckRFC_first;
|
157 |
|
|
wire [13:0] w_MR0, w_MR1, w_MR2;
|
158 |
|
|
|
159 |
|
|
////////
|
160 |
|
|
//
|
161 |
|
|
reg need_refresh, pre_refresh_stall;
|
162 |
|
|
reg refresh_ztimer;
|
163 |
|
|
reg [16:0] refresh_counter;
|
164 |
|
|
reg [2:0] refresh_addr;
|
165 |
|
|
reg [24:0] refresh_instruction;
|
166 |
|
|
|
167 |
|
|
reg [2:0] cmd_pipe;
|
168 |
|
|
reg [1:0] nxt_pipe;
|
169 |
|
|
|
170 |
|
|
|
171 |
|
|
// Our chosen timing doesn't require any more resolution than one
|
172 |
|
|
// bus clock for ODT. (Of course, this really isn't necessary, since
|
173 |
|
|
// we aren't using ODT as per the MRx registers ... but we keep it
|
174 |
|
|
// around in case we change our minds later.)
|
175 |
|
|
reg [2:0] drive_dqs;
|
176 |
|
|
reg [5:0] dqs_pattern;
|
177 |
|
|
reg [8*LANES-1:0] ddr_dm;
|
178 |
|
|
|
179 |
|
|
reg pipe_stall;
|
180 |
|
|
|
181 |
|
|
// The pending transaction
|
182 |
|
|
reg [DW-1:0] r_data;
|
183 |
|
|
reg r_pending, r_we;
|
184 |
|
|
reg [LGNROWS-1:0] r_row;
|
185 |
|
|
reg [LGNBANKS-1:0] r_bank;
|
186 |
|
|
reg [9:0] r_col;
|
187 |
|
|
reg [DW/8-1:0] r_sel;
|
188 |
|
|
|
189 |
|
|
|
190 |
|
|
// The pending transaction, one further into the pipeline. This is
|
191 |
|
|
// the stage where the read/write command is actually given to the
|
192 |
|
|
// interface if we haven't stalled.
|
193 |
|
|
reg [DW-1:0] s_data;
|
194 |
|
|
reg s_pending, s_we;
|
195 |
|
|
reg [LGNROWS-1:0] s_row, s_nxt_row;
|
196 |
|
|
reg [LGNBANKS-1:0] s_bank, s_nxt_bank;
|
197 |
|
|
reg [9:0] s_col;
|
198 |
|
|
reg [DW/8-1:0] s_sel;
|
199 |
|
|
|
200 |
|
|
// Can we preload the next bank?
|
201 |
|
|
reg [LGNROWS-1:0] r_nxt_row;
|
202 |
|
|
reg [LGNBANKS-1:0] r_nxt_bank;
|
203 |
|
|
|
204 |
|
|
// wire w_precharge_all;
|
205 |
|
|
reg [(1<<LGNBANKS)-1:0] bank_status;
|
206 |
|
|
reg [LGNROWS-1:0] bank_address [0:7];
|
207 |
|
|
|
208 |
|
|
reg [(LGFIFOLN-1):0] bus_fifo_head, bus_fifo_tail;
|
209 |
|
|
reg [DW-1:0] bus_fifo_data [0:BUSNOW];
|
210 |
|
|
reg [DW/8-1:0] bus_fifo_sel [0:BUSNOW];
|
211 |
|
|
reg pre_ack;
|
212 |
|
|
|
213 |
|
|
|
214 |
|
|
reg [BUSNOW:0] bus_active, bus_read, bus_ack;
|
215 |
|
|
reg dir_stall;
|
216 |
|
|
|
217 |
|
|
////////////////////////////////////////////////////////////////////////
|
218 |
|
|
//
|
219 |
|
|
//
|
220 |
|
|
// Reset Logic
|
221 |
|
|
//
|
222 |
|
|
//
|
223 |
|
|
////////////////////////////////////////////////////////////////////////
|
224 |
|
|
//
|
225 |
|
|
//
|
226 |
|
|
// Reset logic should be simple, and is given as follows:
|
227 |
|
|
// note that it depends upon a ROM memory, reset_mem, and an address
|
228 |
|
|
// into that memory: reset_address. Each memory location provides
|
229 |
|
|
// either a "command" to the DDR3 SDRAM, or a timer to wait until
|
230 |
|
|
// the next command. Further, the timer commands indicate whether
|
231 |
|
|
// or not the command during the timer is to be set to idle, or whether
|
232 |
|
|
// the command is instead left as it was.
|
233 |
|
|
//
|
234 |
|
|
parameter [24:0] INITIAL_RESET_INSTRUCTION = { 4'h4, DDR_NOOP, 17'd40_000 };
|
235 |
|
|
//
|
236 |
|
|
//
|
237 |
3 |
dgisselq |
initial reset_override = 1'b1;
|
238 |
18 |
dgisselq |
initial reset_address = 4'h0;
|
239 |
21 |
dgisselq |
initial reset_cmd <= { DDR_NOOP, INITIAL_RESET_INSTRUCTION[16:0]};
|
240 |
2 |
dgisselq |
always @(posedge i_clk)
|
241 |
21 |
dgisselq |
if (i_reset)
|
242 |
|
|
begin
|
243 |
|
|
reset_override <= 1'b1;
|
244 |
|
|
reset_cmd <= { DDR_NOOP, INITIAL_RESET_INSTRUCTION[16:0]};
|
245 |
|
|
end else if ((reset_ztimer)&&(reset_override))
|
246 |
|
|
begin
|
247 |
|
|
if (reset_instruction[DDR_RSTDONE])
|
248 |
|
|
reset_override <= 1'b0;
|
249 |
|
|
reset_cmd <= reset_instruction[20:0];
|
250 |
|
|
end
|
251 |
2 |
dgisselq |
|
252 |
4 |
dgisselq |
initial reset_ztimer = 1'b0; // Is the timer zero?
|
253 |
5 |
dgisselq |
initial reset_timer = 17'h02;
|
254 |
2 |
dgisselq |
always @(posedge i_clk)
|
255 |
21 |
dgisselq |
if (i_reset)
|
256 |
|
|
begin
|
257 |
|
|
reset_ztimer <= 1'b0;
|
258 |
|
|
reset_timer <= 17'd2;
|
259 |
|
|
end else if (reset_override)
|
260 |
|
|
begin
|
261 |
|
|
if (!reset_ztimer)
|
262 |
2 |
dgisselq |
begin
|
263 |
|
|
reset_ztimer <= (reset_timer == 17'h01);
|
264 |
21 |
dgisselq |
reset_timer <= reset_timer - 17'h01;
|
265 |
|
|
end else if (reset_instruction[DDR_RSTTIMER])
|
266 |
2 |
dgisselq |
begin
|
267 |
21 |
dgisselq |
reset_ztimer <= (reset_instruction[16:0]==0);
|
268 |
|
|
reset_timer <= reset_instruction[16:0];
|
269 |
2 |
dgisselq |
end
|
270 |
21 |
dgisselq |
end else
|
271 |
|
|
reset_ztimer <= 1'b1;
|
272 |
|
|
|
273 |
2 |
dgisselq |
|
274 |
21 |
dgisselq |
assign w_MR0 = 14'h0210;
|
275 |
|
|
assign w_MR1 = 14'h0044;
|
276 |
|
|
assign w_MR2 = 14'h0040;
|
277 |
|
|
assign w_ckXPR = 17'd12;// Table 68, p186: 56 nCK / 4 sys clks= 14(-2)
|
278 |
18 |
dgisselq |
assign w_ckRFC_first = 17'd11; // i.e. 52 nCK, or ckREFI
|
279 |
21 |
dgisselq |
function [24:0] get_reset_instruction;
|
280 |
|
|
input [3:0] i_addr;
|
281 |
|
|
|
282 |
|
|
// DONE, TIMER, RESET, CKE,
|
283 |
|
|
case(i_addr) // RSTDONE, TIMER, CKE, ??
|
284 |
|
|
//
|
285 |
|
|
// 1. Reset asserted (active low) for 200 us. (@80MHz)
|
286 |
|
|
// INITIAL_RESET_INSTRUCTION = { 4'h4, DDR_NOOP, 17'd40_000 };
|
287 |
|
|
4'h0: get_reset_instruction = { 4'h4, DDR_NOOP, 17'd16_000 };
|
288 |
|
|
//
|
289 |
|
|
// 2. Reset de-asserted, wait 500 us before asserting CKE
|
290 |
|
|
4'h1: get_reset_instruction = { 4'h6, DDR_NOOP, 17'd40_000 };
|
291 |
|
|
//
|
292 |
|
|
// 3. Assert CKE, wait minimum of Reset CKE Exit time
|
293 |
|
|
4'h2: get_reset_instruction = { 4'h7, DDR_NOOP, w_ckXPR };
|
294 |
|
|
//
|
295 |
|
|
// 4. Set MR2. (4 nCK, no TIMER, but needs a NOOP cycle)
|
296 |
|
|
4'h3: get_reset_instruction = { 4'h3, DDR_MRSET, 3'h2, w_MR2 };
|
297 |
|
|
//
|
298 |
|
|
// 5. Set MR1. (4 nCK, no TIMER, but needs a NOOP cycle)
|
299 |
|
|
4'h4: get_reset_instruction = { 4'h3, DDR_MRSET, 3'h1, w_MR1 };
|
300 |
|
|
//
|
301 |
|
|
// 6. Set MR0
|
302 |
|
|
4'h5: get_reset_instruction = { 4'h3, DDR_MRSET, 3'h0, w_MR0 };
|
303 |
|
|
//
|
304 |
|
|
// 7. Wait 12 nCK clocks, or 3 sys clocks
|
305 |
|
|
4'h6: get_reset_instruction = { 4'h7, DDR_NOOP, 17'd1 };
|
306 |
|
|
//
|
307 |
|
|
// 8. Issue a ZQCL command to start ZQ calibration, A10 is high
|
308 |
|
|
4'h7: get_reset_instruction = { 4'h3, DDR_ZQS, 6'h0, 1'b1, 10'h0};
|
309 |
|
|
//
|
310 |
|
|
// 9. Wait for both tDLLK and tZQinit completed, both are
|
311 |
|
|
// 512 cks. Of course, since every one of these commands takes
|
312 |
|
|
// two clocks, we wait for one quarter as many clocks (minus
|
313 |
|
|
// two for our timer logic)
|
314 |
|
|
4'h8: get_reset_instruction = { 4'h7, DDR_NOOP, 17'd126 };
|
315 |
|
|
//
|
316 |
|
|
// 10. Precharge all command
|
317 |
|
|
4'h9: get_reset_instruction = { 4'h3, DDR_PRECHARGE, 6'h0, 1'b1, 10'h0 };
|
318 |
|
|
//
|
319 |
|
|
// 11. Wait 5 memory clocks (8 memory clocks) for the precharge
|
320 |
|
|
// to complete. A single NOOP here will have us waiting
|
321 |
|
|
// 8 clocks, so we should be good here.
|
322 |
|
|
4'ha: get_reset_instruction = { 4'h3, DDR_NOOP, 17'd0 };
|
323 |
|
|
//
|
324 |
|
|
// 12. A single Auto Refresh commands
|
325 |
|
|
4'hb: get_reset_instruction = { 4'h3, DDR_REFRESH, 17'h00 };
|
326 |
|
|
//
|
327 |
|
|
// 13. Wait for the auto refresh to complete
|
328 |
|
|
4'hc: get_reset_instruction = { 4'h7, DDR_NOOP, w_ckRFC_first };
|
329 |
|
|
4'hd: get_reset_instruction = { 4'h7, DDR_NOOP, 17'd3 };
|
330 |
|
|
default:
|
331 |
|
|
get_reset_instruction ={4'hb, DDR_NOOP, 17'd00_000 };
|
332 |
|
|
endcase
|
333 |
|
|
|
334 |
|
|
endfunction
|
335 |
|
|
|
336 |
|
|
initial reset_instruction = INITIAL_RESET_INSTRUCTION;
|
337 |
2 |
dgisselq |
always @(posedge i_clk)
|
338 |
21 |
dgisselq |
if (i_reset)
|
339 |
|
|
reset_instruction <= INITIAL_RESET_INSTRUCTION;
|
340 |
|
|
else if (reset_ztimer)
|
341 |
|
|
reset_instruction <= get_reset_instruction(reset_address);
|
342 |
2 |
dgisselq |
|
343 |
18 |
dgisselq |
initial reset_address = 4'h0;
|
344 |
2 |
dgisselq |
always @(posedge i_clk)
|
345 |
21 |
dgisselq |
if (i_reset)
|
346 |
|
|
reset_address <= 4'h0;
|
347 |
|
|
else if (reset_ztimer && reset_override &&
|
348 |
|
|
!reset_instruction[DDR_RSTDONE])
|
349 |
|
|
reset_address <= reset_address + 4'h1;
|
350 |
16 |
dgisselq |
|
351 |
21 |
dgisselq |
////////////////////////////////////////////////////////////////////////
|
352 |
|
|
//
|
353 |
|
|
//
|
354 |
|
|
// Refresh Logic
|
355 |
|
|
//
|
356 |
|
|
//
|
357 |
|
|
////////////////////////////////////////////////////////////////////////
|
358 |
|
|
//
|
359 |
|
|
//
|
360 |
|
|
//
|
361 |
|
|
// Okay, let's investigate when we need to do a refresh. Our plan
|
362 |
|
|
// will be to do a single refreshes every tREFI seconds. We will not
|
363 |
|
|
// push off refreshes, nor pull them in--for simplicity.
|
364 |
|
|
// tREFI = 7.8us, but it is a parameter in the number of clocks
|
365 |
|
|
// (2496 nCK). In our case,
|
366 |
|
|
// 7.8us / 12.5ns = 624 clocks (not nCK!)
|
367 |
|
|
//
|
368 |
|
|
// Note that 160ns are needed between refresh commands (JEDEC, p172),
|
369 |
|
|
// or 52 clocks @320MHz. After this time, no more refreshes will be
|
370 |
|
|
// needed for (2496-52) clocks (@ 320 MHz), or (624-13) clocks (@80MHz).
|
371 |
|
|
//
|
372 |
|
|
// This logic is very similar to the refresh logic, both use a memory
|
373 |
|
|
// as a script.
|
374 |
|
|
//
|
375 |
|
|
initial refresh_addr = 3'h0;
|
376 |
16 |
dgisselq |
always @(posedge i_clk)
|
377 |
21 |
dgisselq |
if (reset_override)
|
378 |
|
|
refresh_addr <= 3'h0;
|
379 |
|
|
else if (refresh_ztimer)
|
380 |
|
|
refresh_addr <= refresh_addr + 3'h1;
|
381 |
|
|
else if (refresh_instruction[DDR_RFBEGIN])
|
382 |
|
|
refresh_addr <= 3'h0;
|
383 |
2 |
dgisselq |
|
384 |
21 |
dgisselq |
initial refresh_ztimer = 1'b0;
|
385 |
|
|
initial refresh_counter = 17'd4;
|
386 |
16 |
dgisselq |
always @(posedge i_clk)
|
387 |
21 |
dgisselq |
if (reset_override)
|
388 |
|
|
begin
|
389 |
|
|
refresh_ztimer <= 1'b0;
|
390 |
|
|
refresh_counter <= 17'd4;
|
391 |
|
|
end else if (!refresh_ztimer)
|
392 |
|
|
begin
|
393 |
|
|
refresh_ztimer <= (refresh_counter == 17'h1);
|
394 |
|
|
refresh_counter <= (refresh_counter - 17'h1);
|
395 |
|
|
end else if (refresh_instruction[DDR_RFTIMER])
|
396 |
|
|
begin
|
397 |
|
|
refresh_ztimer <= (refresh_instruction[16:0] == 0);
|
398 |
|
|
refresh_counter <= refresh_instruction[16:0];
|
399 |
|
|
end
|
400 |
2 |
dgisselq |
|
401 |
16 |
dgisselq |
// We need to wait for the bus to become idle from whatever state
|
402 |
|
|
// it is in. The difficult time for this measurement is assuming
|
403 |
|
|
// a write was just given. In that case, we need to wait for the
|
404 |
|
|
// write to complete, and then to wait an additional tWR (write
|
405 |
|
|
// recovery time) or 6 nCK clocks from the end of the write. This
|
406 |
|
|
// works out to seven idle bus cycles from the time of the write
|
407 |
|
|
// command, or a count of 5 (7-2).
|
408 |
21 |
dgisselq |
localparam [16:0] PRE_STALL_COUNTS = 17'd3;
|
409 |
|
|
localparam [16:0] WAIT_FOR_IDLE = 0;
|
410 |
|
|
localparam [16:0] PRIOR_WAIT = 13;
|
411 |
|
|
localparam [16:0] REFRESH_INTERVAL = 624;
|
412 |
|
|
|
413 |
|
|
localparam [16:0] w_ckREFI_left = REFRESH_INTERVAL
|
414 |
|
|
- PRIOR_WAIT // Minus what we've already waited
|
415 |
|
|
- WAIT_FOR_IDLE
|
416 |
18 |
dgisselq |
-17'd19;
|
417 |
21 |
dgisselq |
localparam [16:0] w_ckRFC_nxt = 17'd12-17'd3;
|
418 |
16 |
dgisselq |
|
419 |
21 |
dgisselq |
localparam w_wait_for_idle = WAIT_FOR_IDLE;
|
420 |
|
|
localparam w_pre_stall_counts = PRE_STALL_COUNTS;
|
421 |
|
|
|
422 |
|
|
|
423 |
|
|
parameter [24:0] INITIAL_REFRESH_INSTRUCTION = { 4'h2, DDR_NOOP, 17'd1 };
|
424 |
|
|
function [24:0] get_refresh_instruction;
|
425 |
|
|
input [2:0] i_refaddr;
|
426 |
|
|
|
427 |
|
|
case(i_refaddr)
|
428 |
|
|
// Bit fields are:
|
429 |
|
|
// NEED-REFRESH, HAVE-TIMER, BEGIN(start-over)
|
430 |
|
|
// DDR_PREREFRESH_STALL = 24;
|
431 |
|
|
// DDR_NEEDREFRESH = 23;
|
432 |
|
|
// DDR_RFTIMER = 22;
|
433 |
|
|
// DDR_RFBEGIN = 21;
|
434 |
|
|
// Command, 20:17
|
435 |
|
|
// timer value, 16:0
|
436 |
|
|
//
|
437 |
16 |
dgisselq |
// First, a number of clocks needing no refresh
|
438 |
21 |
dgisselq |
3'h0: get_refresh_instruction = { 4'h2, DDR_NOOP, w_ckREFI_left };
|
439 |
16 |
dgisselq |
// Then, we take command of the bus and wait for it to be
|
440 |
|
|
// guaranteed idle
|
441 |
21 |
dgisselq |
3'h1: get_refresh_instruction = { 4'ha, DDR_NOOP, w_pre_stall_counts };
|
442 |
|
|
3'h2: get_refresh_instruction = { 4'hc, DDR_NOOP, w_wait_for_idle };
|
443 |
16 |
dgisselq |
// Once the bus is idle, all commands complete, and a minimum
|
444 |
|
|
// recovery time given, we can issue a precharge all command
|
445 |
21 |
dgisselq |
3'h3: get_refresh_instruction = { 4'hc, DDR_PRECHARGE, 17'h0400 };
|
446 |
16 |
dgisselq |
// Now we need to wait tRP = 3 clocks (6 nCK)
|
447 |
21 |
dgisselq |
3'h4: get_refresh_instruction = { 4'hc, DDR_NOOP, 17'h00 };
|
448 |
|
|
3'h5: get_refresh_instruction = { 4'hc, DDR_REFRESH, 17'h00 };
|
449 |
|
|
3'h6: get_refresh_instruction = { 4'he, DDR_NOOP, w_ckRFC_nxt };
|
450 |
|
|
3'h7: get_refresh_instruction = { 4'h2, DDR_NOOP, 17'd12 };
|
451 |
18 |
dgisselq |
// default:
|
452 |
21 |
dgisselq |
// refresh_instruction = { 4'h1, DDR_NOOP, 17'h00 };
|
453 |
16 |
dgisselq |
endcase
|
454 |
21 |
dgisselq |
endfunction
|
455 |
16 |
dgisselq |
|
456 |
21 |
dgisselq |
initial refresh_instruction = INITIAL_REFRESH_INSTRUCTION;
|
457 |
|
|
always @(posedge i_clk)
|
458 |
|
|
if (reset_override)
|
459 |
|
|
// refresh_instruction <= { 4'h2, DDR_NOOP, 17'd1 };
|
460 |
|
|
refresh_instruction <= INITIAL_REFRESH_INSTRUCTION;
|
461 |
|
|
else if (refresh_ztimer)
|
462 |
|
|
refresh_instruction <= get_refresh_instruction(refresh_addr);
|
463 |
|
|
|
464 |
16 |
dgisselq |
// Note that we don't need to check if (reset_override) here since
|
465 |
|
|
// refresh_ztimer will always be true if (reset_override)--in other
|
466 |
|
|
// words, it will be true for many, many, clocks--enough for this
|
467 |
|
|
// logic to settle out.
|
468 |
21 |
dgisselq |
initial refresh_cmd = INITIAL_REFRESH_INSTRUCTION[20:0];
|
469 |
16 |
dgisselq |
always @(posedge i_clk)
|
470 |
21 |
dgisselq |
if (reset_override)
|
471 |
|
|
refresh_cmd <= INITIAL_REFRESH_INSTRUCTION[20:0];
|
472 |
|
|
else if (refresh_ztimer)
|
473 |
|
|
refresh_cmd <= refresh_instruction[20:0];
|
474 |
|
|
|
475 |
|
|
initial need_refresh = INITIAL_REFRESH_INSTRUCTION[DDR_NEEDREFRESH];
|
476 |
16 |
dgisselq |
always @(posedge i_clk)
|
477 |
21 |
dgisselq |
if (reset_override)
|
478 |
|
|
need_refresh <= INITIAL_REFRESH_INSTRUCTION[DDR_NEEDREFRESH];
|
479 |
|
|
else if (refresh_ztimer)
|
480 |
|
|
need_refresh <= refresh_instruction[DDR_NEEDREFRESH];
|
481 |
|
|
|
482 |
|
|
initial pre_refresh_stall = 1'b0;
|
483 |
18 |
dgisselq |
always @(posedge i_clk)
|
484 |
21 |
dgisselq |
if (reset_override)
|
485 |
|
|
pre_refresh_stall <= 1'b0;
|
486 |
|
|
else if (refresh_ztimer)
|
487 |
|
|
pre_refresh_stall <= refresh_instruction[DDR_PREREFRESH_STALL];
|
488 |
16 |
dgisselq |
|
489 |
|
|
|
490 |
|
|
|
491 |
|
|
|
492 |
21 |
dgisselq |
////////////////////////////////////////////////////////////////////////
|
493 |
|
|
//
|
494 |
|
|
//
|
495 |
|
|
// Open Banks
|
496 |
|
|
//
|
497 |
|
|
//
|
498 |
|
|
////////////////////////////////////////////////////////////////////////
|
499 |
|
|
//
|
500 |
|
|
//
|
501 |
|
|
//
|
502 |
|
|
// Let's keep track of any open banks. There are 8 of them to keep
|
503 |
|
|
// track of.
|
504 |
|
|
//
|
505 |
|
|
// A precharge requires 1 clocks at 80MHz to complete.
|
506 |
|
|
// An activate also requires 1 clocks at 80MHz to complete.
|
507 |
|
|
// By the time we log these, they will be complete.
|
508 |
|
|
// Precharges are not allowed until the maximum of:
|
509 |
|
|
// 2 clocks (200 MHz) after a read command
|
510 |
|
|
// 4 clocks after a write command
|
511 |
|
|
//
|
512 |
|
|
//
|
513 |
|
|
initial begin
|
514 |
|
|
for(ik=0; ik< (1<<LGNBANKS); ik=ik+1)
|
515 |
|
|
begin
|
516 |
|
|
bank_status[ik] = 0;
|
517 |
|
|
bank_address[ik] = 0;
|
518 |
|
|
end
|
519 |
|
|
end
|
520 |
16 |
dgisselq |
|
521 |
2 |
dgisselq |
always @(posedge i_clk)
|
522 |
|
|
begin
|
523 |
18 |
dgisselq |
if (cmd_pipe[0])
|
524 |
|
|
begin
|
525 |
|
|
bank_status[s_bank] <= 1'b0;
|
526 |
|
|
if (nxt_pipe[1])
|
527 |
|
|
bank_status[s_nxt_bank] <= 1'b1;
|
528 |
|
|
end else begin
|
529 |
|
|
if (cmd_pipe[1])
|
530 |
|
|
bank_status[s_bank] <= 1'b1;
|
531 |
|
|
else if (nxt_pipe[1])
|
532 |
|
|
bank_status[s_nxt_bank] <= 1'b1;
|
533 |
|
|
if (nxt_pipe[0])
|
534 |
|
|
bank_status[s_nxt_bank] <= 1'b0;
|
535 |
|
|
end
|
536 |
|
|
|
537 |
21 |
dgisselq |
if (i_reset || maintenance_override)
|
538 |
2 |
dgisselq |
begin
|
539 |
21 |
dgisselq |
// All banks get precharged on any refresh
|
540 |
|
|
// (or reset) event
|
541 |
|
|
//
|
542 |
|
|
for(ik = 0; ik < (1<<LGNBANKS); ik = ik+1)
|
543 |
|
|
bank_status[ik] <= 0;
|
544 |
2 |
dgisselq |
end
|
545 |
18 |
dgisselq |
|
546 |
2 |
dgisselq |
end
|
547 |
|
|
|
548 |
21 |
dgisselq |
`ifdef FORMAL
|
549 |
|
|
always @(*)
|
550 |
|
|
assert(nxt_pipe != 2'b11);
|
551 |
|
|
`endif
|
552 |
|
|
|
553 |
2 |
dgisselq |
always @(posedge i_clk)
|
554 |
21 |
dgisselq |
if (cmd_pipe[1])
|
555 |
|
|
bank_address[s_bank] <= s_row;
|
556 |
|
|
else if (nxt_pipe[1])
|
557 |
|
|
bank_address[s_nxt_bank] <= s_nxt_row;
|
558 |
2 |
dgisselq |
|
559 |
21 |
dgisselq |
////////////////////////////////////////////////////////////////////////
|
560 |
|
|
//
|
561 |
|
|
//
|
562 |
|
|
// Data BUS information
|
563 |
|
|
//
|
564 |
|
|
//
|
565 |
|
|
////////////////////////////////////////////////////////////////////////
|
566 |
|
|
//
|
567 |
|
|
//
|
568 |
|
|
// Our purpose here is to keep track of when the data bus will be
|
569 |
|
|
// active. This is separate from the FIFO which will contain the
|
570 |
|
|
// data to be placed on the bus (when so placed), in that this is
|
571 |
|
|
// a group of shift registers--every position has a location in
|
572 |
|
|
// time, and time always moves forward. The FIFO, on the other
|
573 |
|
|
// hand, only moves forward when data moves onto the bus.
|
574 |
|
|
//
|
575 |
|
|
//
|
576 |
3 |
dgisselq |
initial bus_active = 0;
|
577 |
14 |
dgisselq |
initial bus_ack = 0;
|
578 |
2 |
dgisselq |
always @(posedge i_clk)
|
579 |
|
|
begin
|
580 |
16 |
dgisselq |
bus_active[BUSNOW:0] <= { bus_active[(BUSNOW-1):0], 1'b0 };
|
581 |
|
|
// Drive the d-bus?
|
582 |
|
|
bus_read[BUSNOW:0] <= { bus_read[(BUSNOW-1):0], 1'b0 };
|
583 |
13 |
dgisselq |
// Will this position on the bus get a wishbone acknowledgement?
|
584 |
16 |
dgisselq |
bus_ack[BUSNOW:0] <= { bus_ack[(BUSNOW-1):0], 1'b0 };
|
585 |
13 |
dgisselq |
|
586 |
21 |
dgisselq |
if (cmd_pipe[2]) // && !i_reset && i_wb_cyc)
|
587 |
2 |
dgisselq |
begin
|
588 |
18 |
dgisselq |
bus_active[0]<= 1'b1; // Data transfers in one clocks
|
589 |
|
|
bus_ack[0] <= 1'b1;
|
590 |
4 |
dgisselq |
|
591 |
19 |
dgisselq |
bus_read[0] <= !s_we;
|
592 |
2 |
dgisselq |
end
|
593 |
21 |
dgisselq |
|
594 |
|
|
if (i_reset || !i_wb_cyc)
|
595 |
|
|
bus_ack <= 0;
|
596 |
2 |
dgisselq |
end
|
597 |
|
|
|
598 |
21 |
dgisselq |
//
|
599 |
|
|
//
|
600 |
|
|
// Can we issue a read command?
|
601 |
|
|
//
|
602 |
|
|
//
|
603 |
|
|
initial { r_pending, s_pending, pipe_stall, o_wb_stall } = 4'b0001;
|
604 |
|
|
initial nxt_pipe = 0;
|
605 |
|
|
initial cmd_pipe = 0;
|
606 |
|
|
initial dir_stall = 0;
|
607 |
2 |
dgisselq |
always @(posedge i_clk)
|
608 |
|
|
begin
|
609 |
21 |
dgisselq |
r_pending <= (i_wb_stb)&&(!o_wb_stall)
|
610 |
9 |
dgisselq |
||(r_pending)&&(pipe_stall);
|
611 |
21 |
dgisselq |
dir_stall <= (i_wb_stb && !o_wb_stall && r_pending
|
612 |
|
|
&& r_we != i_wb_we);
|
613 |
|
|
if (pipe_stall && dir_stall)
|
614 |
|
|
dir_stall <= 1;
|
615 |
|
|
|
616 |
|
|
if (!pipe_stall && !dir_stall)
|
617 |
9 |
dgisselq |
s_pending <= r_pending;
|
618 |
21 |
dgisselq |
if (!pipe_stall && !dir_stall)
|
619 |
2 |
dgisselq |
begin
|
620 |
18 |
dgisselq |
if (r_pending)
|
621 |
|
|
begin
|
622 |
|
|
pipe_stall <= 1'b1;
|
623 |
21 |
dgisselq |
o_wb_stall <= i_wb_stb;
|
624 |
|
|
/*
|
625 |
|
|
// Won't happen. pipe_stall = |cmd_pipe[1:0]
|
626 |
|
|
if (cmd_pipe[1] && s_bank == r_bank
|
627 |
|
|
&& s_row == r_row)
|
628 |
|
|
cmd_pipe <= 3'b100;
|
629 |
|
|
else
|
630 |
|
|
*/
|
631 |
|
|
if (nxt_pipe[1] && s_nxt_bank == r_bank
|
632 |
|
|
&& s_nxt_row == r_row)
|
633 |
|
|
begin
|
634 |
|
|
// Row was just activated via nxt_pipe,
|
635 |
|
|
// we can proceed immediately with
|
636 |
|
|
/// reading or writing
|
637 |
|
|
cmd_pipe <= 3'b100;
|
638 |
|
|
pipe_stall <= 1'b0;
|
639 |
|
|
o_wb_stall <= 1'b0;
|
640 |
|
|
end else if (nxt_pipe[0]&& s_nxt_bank == r_bank)
|
641 |
|
|
// Row is deactivated, and must be
|
642 |
|
|
// activated
|
643 |
18 |
dgisselq |
cmd_pipe <= 3'b010;
|
644 |
21 |
dgisselq |
else if (!bank_status[r_bank]
|
645 |
|
|
&&(!nxt_pipe[1]
|
646 |
|
|
|| s_nxt_bank != r_bank))
|
647 |
|
|
// Row is deactivated, and must be
|
648 |
|
|
// activated
|
649 |
|
|
cmd_pipe <= 3'b010;
|
650 |
|
|
else if((bank_address[r_bank] != r_row
|
651 |
|
|
||(nxt_pipe[1]
|
652 |
|
|
&& s_nxt_bank == r_bank)
|
653 |
|
|
&& s_nxt_row != r_row))
|
654 |
|
|
begin
|
655 |
|
|
// The wrong row is activated. We
|
656 |
|
|
// must precharge this row and
|
657 |
|
|
// then activate it on the next cycle
|
658 |
18 |
dgisselq |
cmd_pipe <= 3'b001; // Read in two clocks
|
659 |
21 |
dgisselq |
|
660 |
|
|
// If the "nxt_pipe" logic just handled
|
661 |
|
|
// deactivating this row, then
|
662 |
|
|
// go directly to activating the right
|
663 |
|
|
// row
|
664 |
|
|
if (nxt_pipe[0] && (s_nxt_bank == r_bank))
|
665 |
|
|
cmd_pipe <= 3'b010;
|
666 |
|
|
end else begin
|
667 |
18 |
dgisselq |
cmd_pipe <= 3'b100; // Read now
|
668 |
|
|
pipe_stall <= 1'b0;
|
669 |
|
|
o_wb_stall <= 1'b0;
|
670 |
|
|
end
|
671 |
|
|
|
672 |
21 |
dgisselq |
if (!bank_status[r_nxt_bank])
|
673 |
18 |
dgisselq |
nxt_pipe <= 2'b10;
|
674 |
|
|
else if (bank_address[r_nxt_bank] != r_row)
|
675 |
|
|
nxt_pipe <= 2'b01; // Read in two clocks
|
676 |
|
|
else
|
677 |
|
|
nxt_pipe <= 2'b00; // Next is ready
|
678 |
|
|
if (nxt_pipe[1])
|
679 |
|
|
nxt_pipe[1] <= 1'b0;
|
680 |
|
|
end else begin
|
681 |
|
|
cmd_pipe <= 3'b000;
|
682 |
|
|
nxt_pipe <= { nxt_pipe[0], 1'b0 };
|
683 |
|
|
pipe_stall <= 1'b0;
|
684 |
|
|
o_wb_stall <= 1'b0;
|
685 |
|
|
end
|
686 |
9 |
dgisselq |
end else begin // if (pipe_stall)
|
687 |
18 |
dgisselq |
pipe_stall <= (s_pending)&&(cmd_pipe[0]);
|
688 |
21 |
dgisselq |
if (!r_pending)
|
689 |
|
|
o_wb_stall <= i_wb_stb;
|
690 |
|
|
else
|
691 |
|
|
o_wb_stall <= (s_pending)&&(cmd_pipe[0]);
|
692 |
18 |
dgisselq |
cmd_pipe <= { cmd_pipe[1:0], 1'b0 };
|
693 |
|
|
|
694 |
21 |
dgisselq |
if ((cmd_pipe[1:0] & nxt_pipe) != 2'b00)
|
695 |
|
|
nxt_pipe <= nxt_pipe;
|
696 |
|
|
else
|
697 |
|
|
nxt_pipe <= nxt_pipe << 1;
|
698 |
9 |
dgisselq |
end
|
699 |
21 |
dgisselq |
|
700 |
18 |
dgisselq |
if (pre_refresh_stall)
|
701 |
2 |
dgisselq |
o_wb_stall <= 1'b1;
|
702 |
|
|
|
703 |
21 |
dgisselq |
if (need_refresh)
|
704 |
|
|
nxt_pipe <= 0;
|
705 |
|
|
|
706 |
|
|
if (!o_wb_stall)
|
707 |
2 |
dgisselq |
begin
|
708 |
|
|
r_we <= i_wb_we;
|
709 |
|
|
r_data <= i_wb_data;
|
710 |
18 |
dgisselq |
r_row <= i_wb_addr[23:10]; // 14 bits row address
|
711 |
|
|
r_bank <= i_wb_addr[9:7];
|
712 |
|
|
r_col <= { i_wb_addr[6:0], 3'b000 }; // 10 bits Caddr
|
713 |
16 |
dgisselq |
r_sel <= i_wb_sel;
|
714 |
2 |
dgisselq |
|
715 |
16 |
dgisselq |
// i_wb_addr[0] is the 8-bit byte selector of 16-bits (ignored)
|
716 |
|
|
// i_wb_addr[1] is the 16-bit half-word selector of 32-bits (ignored)
|
717 |
|
|
// i_wb_addr[2] is the 32-bit word selector of 64-bits (ignored)
|
718 |
|
|
// i_wb_addr[3] is the 64-bit long word selector of 128-bits
|
719 |
|
|
|
720 |
2 |
dgisselq |
// pre-emptive work
|
721 |
21 |
dgisselq |
{ r_nxt_row, r_nxt_bank } <= i_wb_addr[23:7] + 1;
|
722 |
2 |
dgisselq |
end
|
723 |
9 |
dgisselq |
|
724 |
21 |
dgisselq |
if (!pipe_stall)
|
725 |
9 |
dgisselq |
begin
|
726 |
|
|
// Moving one down the pipeline
|
727 |
|
|
s_we <= r_we;
|
728 |
|
|
s_data <= r_data;
|
729 |
|
|
s_row <= r_row;
|
730 |
|
|
s_bank <= r_bank;
|
731 |
|
|
s_col <= r_col;
|
732 |
21 |
dgisselq |
s_sel <= (r_we) ? (~r_sel):16'h00;
|
733 |
9 |
dgisselq |
|
734 |
21 |
dgisselq |
if (r_pending)
|
735 |
|
|
begin
|
736 |
|
|
// pre-emptive work
|
737 |
|
|
s_nxt_row <= r_nxt_row;
|
738 |
|
|
s_nxt_bank <= r_nxt_bank;
|
739 |
|
|
end
|
740 |
9 |
dgisselq |
end
|
741 |
21 |
dgisselq |
|
742 |
|
|
if (i_reset || !i_wb_cyc)
|
743 |
|
|
begin
|
744 |
|
|
r_pending <= 1'b0;
|
745 |
|
|
s_pending <= 1'b0;
|
746 |
|
|
cmd_pipe <= 0;
|
747 |
|
|
nxt_pipe <= 0;
|
748 |
|
|
pipe_stall <= 0;
|
749 |
|
|
end
|
750 |
|
|
|
751 |
|
|
if (i_reset || reset_override)
|
752 |
|
|
o_wb_stall <= 1'b1;
|
753 |
2 |
dgisselq |
end
|
754 |
|
|
|
755 |
21 |
dgisselq |
//
|
756 |
|
|
//
|
757 |
|
|
// Okay, let's look at the last assignment in our chain. It should
|
758 |
|
|
// look something like:
|
759 |
|
|
initial o_ddr_reset_n = 1'b0;
|
760 |
|
|
always @(posedge i_clk)
|
761 |
|
|
if (i_reset)
|
762 |
|
|
o_ddr_reset_n <= 1'b0;
|
763 |
|
|
else if (reset_ztimer)
|
764 |
|
|
o_ddr_reset_n <= reset_instruction[DDR_RSTBIT];
|
765 |
3 |
dgisselq |
|
766 |
21 |
dgisselq |
initial o_ddr_cke = 1'b0;
|
767 |
2 |
dgisselq |
always @(posedge i_clk)
|
768 |
21 |
dgisselq |
if (i_reset)
|
769 |
|
|
o_ddr_cke <= 1'b0;
|
770 |
|
|
else if (reset_ztimer)
|
771 |
|
|
o_ddr_cke <= reset_instruction[DDR_CKEBIT];
|
772 |
6 |
dgisselq |
|
773 |
21 |
dgisselq |
initial maintenance_override = 1'b1;
|
774 |
9 |
dgisselq |
always @(posedge i_clk)
|
775 |
21 |
dgisselq |
if (i_reset)
|
776 |
|
|
maintenance_override <= 1'b1;
|
777 |
|
|
else
|
778 |
|
|
maintenance_override <= (reset_override)||(need_refresh);
|
779 |
7 |
dgisselq |
|
780 |
21 |
dgisselq |
initial maintenance_cmd = { DDR_NOOP, 17'h00 };
|
781 |
9 |
dgisselq |
always @(posedge i_clk)
|
782 |
21 |
dgisselq |
if (i_reset)
|
783 |
|
|
maintenance_cmd <= { DDR_NOOP, 17'h00 };
|
784 |
|
|
else
|
785 |
|
|
maintenance_cmd <= (reset_override) ? reset_cmd:refresh_cmd;
|
786 |
9 |
dgisselq |
|
787 |
18 |
dgisselq |
|
788 |
21 |
dgisselq |
initial cmd_a = 0;
|
789 |
|
|
initial cmd_b = 0;
|
790 |
|
|
initial cmd_c = 0;
|
791 |
|
|
initial cmd_d = 0;
|
792 |
2 |
dgisselq |
always @(posedge i_clk)
|
793 |
|
|
begin
|
794 |
18 |
dgisselq |
// We run our commands by timeslots, A, B, C, and D in that
|
795 |
|
|
// order.
|
796 |
|
|
|
797 |
21 |
dgisselq |
// Timeslot A always contains any maintenance commands we
|
798 |
|
|
// might have.
|
799 |
18 |
dgisselq |
// Timeslot B always contains any precharge command, excluding
|
800 |
|
|
// the maintenance precharge-all command.
|
801 |
|
|
// Timeslot C always contains any activate command
|
802 |
|
|
// Timeslot D always contains any read/write command
|
803 |
|
|
//
|
804 |
|
|
// We can always set these commands to whatever, to reduce the
|
805 |
|
|
// used logic, as long as the top bit (CS_N) is used to select
|
806 |
|
|
// whether or not the command is active. If CS_N is 0 the
|
807 |
|
|
// command will be applied by the chip, if 1 the command turns
|
808 |
|
|
// into a deselect command that the chip will ignore.
|
809 |
|
|
//
|
810 |
|
|
cmd_a <= maintenance_cmd;
|
811 |
|
|
|
812 |
21 |
dgisselq |
cmd_b <= { DDR_PRECHARGE, s_nxt_bank, s_nxt_row[LGNROWS-1:11],
|
813 |
|
|
1'b0, s_nxt_row[9:0] };
|
814 |
|
|
cmd_b[DDR_CSBIT] <= 1'b1; // Deactivate, unless ...
|
815 |
18 |
dgisselq |
if (cmd_pipe[0])
|
816 |
21 |
dgisselq |
cmd_b <= { DDR_PRECHARGE, s_bank, s_row[LGNROWS-1:11],
|
817 |
|
|
1'b0, s_row[9:0] };
|
818 |
|
|
cmd_b[DDR_CSBIT] <= (!cmd_pipe[0])&&(!nxt_pipe[0]);
|
819 |
18 |
dgisselq |
|
820 |
21 |
dgisselq |
// Prevent us from deactivating the same bank twice by
|
821 |
|
|
// accident
|
822 |
|
|
if (cmd_pipe[0] && !bank_status[s_bank])
|
823 |
|
|
cmd_b[DDR_CSBIT] <= 1; // Disable
|
824 |
|
|
else if (!cmd_pipe[0]&& nxt_pipe[0] && !bank_status[s_nxt_bank])
|
825 |
|
|
cmd_b[DDR_CSBIT] <= 1; // Disable
|
826 |
|
|
|
827 |
|
|
|
828 |
|
|
//
|
829 |
|
|
// 3rd position: Activate a row, either the next one,
|
830 |
|
|
// or the one we currently need and are already waiting on
|
831 |
|
|
//
|
832 |
|
|
cmd_c <= { DDR_ACTIVATE, s_nxt_bank, s_nxt_row[LGNROWS-1:0] };
|
833 |
|
|
cmd_c[DDR_CSBIT] <= 1'b1; // Disable command, unless ...
|
834 |
|
|
|
835 |
18 |
dgisselq |
if (cmd_pipe[1])
|
836 |
21 |
dgisselq |
cmd_c <= { DDR_ACTIVATE, s_bank, s_row[LGNROWS-1:0] };
|
837 |
18 |
dgisselq |
else if (nxt_pipe[1])
|
838 |
21 |
dgisselq |
cmd_c[DDR_CSBIT] <= 1'b0;
|
839 |
18 |
dgisselq |
|
840 |
21 |
dgisselq |
//
|
841 |
|
|
// 4th position: Actually issue any read/write commands
|
842 |
|
|
//
|
843 |
|
|
cmd_d[DDR_CSBIT:DDR_WEBIT]<= (s_we)? DDR_WRITE:DDR_READ;
|
844 |
|
|
cmd_d[DDR_WEBIT-1:0] <= { s_bank, 3'h0, 1'b0, s_col };
|
845 |
|
|
cmd_d[DDR_CSBIT] <= !cmd_pipe[2];
|
846 |
18 |
dgisselq |
|
847 |
|
|
|
848 |
|
|
// Now, if the maintenance mode must override whatever we are
|
849 |
|
|
// doing, we only need to apply this more complicated logic
|
850 |
|
|
// to the CS_N bit, or bit[20], since this will activate or
|
851 |
|
|
// deactivate the rest of the command--making the rest
|
852 |
|
|
// either relevant (CS_N=0) or irrelevant (CS_N=1) as we need.
|
853 |
21 |
dgisselq |
if (!i_wb_cyc)
|
854 |
|
|
cmd_d[DDR_CSBIT] <= 1'b1;
|
855 |
|
|
|
856 |
16 |
dgisselq |
if (maintenance_override)
|
857 |
21 |
dgisselq |
begin
|
858 |
|
|
cmd_a[DDR_CSBIT] <= 1'b0;
|
859 |
|
|
// cmd_b[DDR_CSBIT] <= 1'b1;
|
860 |
|
|
// cmd_c[DDR_CSBIT] <= 1'b1;
|
861 |
|
|
// cmd_d[DDR_CSBIT] <= 1'b1;
|
862 |
2 |
dgisselq |
end else
|
863 |
21 |
dgisselq |
cmd_a[DDR_CSBIT] <= 1'b1; // Disable maintenance timeslot
|
864 |
|
|
|
865 |
|
|
if (i_reset)
|
866 |
|
|
begin
|
867 |
|
|
cmd_a[DDR_CSBIT] <= 1'b1;
|
868 |
|
|
cmd_b[DDR_CSBIT] <= 1'b1;
|
869 |
|
|
cmd_c[DDR_CSBIT] <= 1'b1;
|
870 |
|
|
cmd_d[DDR_CSBIT] <= 1'b1;
|
871 |
|
|
end
|
872 |
2 |
dgisselq |
end
|
873 |
|
|
|
874 |
7 |
dgisselq |
// The bus R/W FIFO
|
875 |
21 |
dgisselq |
initial for(jk=0; jk<=BUSNOW; jk=jk+1)
|
876 |
|
|
{ bus_fifo_data[jk], bus_fifo_sel[jk] } = 0;
|
877 |
7 |
dgisselq |
always @(posedge i_clk)
|
878 |
|
|
begin
|
879 |
21 |
dgisselq |
for(ik=1; ik<=BUSNOW; ik=ik+1)
|
880 |
7 |
dgisselq |
begin
|
881 |
21 |
dgisselq |
{ bus_fifo_sel[BUSNOW-ik+1], bus_fifo_data[BUSNOW-ik+1] }
|
882 |
|
|
<= { bus_fifo_sel[BUSNOW-ik], bus_fifo_data[BUSNOW-ik] };
|
883 |
|
|
end
|
884 |
7 |
dgisselq |
|
885 |
21 |
dgisselq |
{ bus_fifo_data[0], bus_fifo_sel[0] } <= { s_data, s_sel };
|
886 |
|
|
if (!s_pending || pipe_stall)
|
887 |
|
|
bus_fifo_sel[0] <= 0;
|
888 |
7 |
dgisselq |
end
|
889 |
|
|
|
890 |
21 |
dgisselq |
always @(posedge i_clk)
|
891 |
|
|
o_ddr_data <= bus_fifo_data[BUSREG];
|
892 |
7 |
dgisselq |
|
893 |
21 |
dgisselq |
initial ddr_dm = -1;
|
894 |
7 |
dgisselq |
always @(posedge i_clk)
|
895 |
21 |
dgisselq |
ddr_dm <= (bus_ack[BUSREG])? bus_fifo_sel[BUSREG]
|
896 |
|
|
: (!bus_read[BUSREG] ? {(8*LANES){1'b1}}: {(8*LANES){1'b0}});
|
897 |
|
|
|
898 |
|
|
initial drive_dqs = 0;
|
899 |
16 |
dgisselq |
always @(posedge i_clk)
|
900 |
18 |
dgisselq |
begin
|
901 |
|
|
drive_dqs[1] <= (bus_active[(BUSREG)])
|
902 |
|
|
&&(!bus_read[(BUSREG)]);
|
903 |
|
|
drive_dqs[0] <= (bus_active[BUSREG:(BUSREG-1)] != 2'b00)
|
904 |
|
|
&&(bus_read[BUSREG:(BUSREG-1)] == 2'b00);
|
905 |
|
|
//
|
906 |
21 |
dgisselq |
drive_dqs[2] <= (bus_active[(BUSREG)])&&(!bus_read[(BUSREG)])
|
907 |
|
|
// Add a postamble ... if we drove DQS in the
|
908 |
|
|
// last clock, then drive it now
|
909 |
|
|
||drive_dqs[1];
|
910 |
|
|
|
911 |
|
|
dqs_pattern[5:4] <= 2'b11;
|
912 |
|
|
dqs_pattern[3:2] <= 2'b10;
|
913 |
|
|
dqs_pattern[1:0] <= 2'b00;
|
914 |
|
|
|
915 |
|
|
if (bus_active[BUSREG]&& !bus_read[BUSREG])
|
916 |
|
|
begin
|
917 |
|
|
dqs_pattern[5:4] <= 2'b10;
|
918 |
|
|
dqs_pattern[1:0] <= 2'b10;
|
919 |
|
|
end
|
920 |
18 |
dgisselq |
end
|
921 |
2 |
dgisselq |
|
922 |
18 |
dgisselq |
// First command
|
923 |
21 |
dgisselq |
assign o_ddr_cmd_a = {cmd_a,drive_dqs[2],ddr_dm[6*LANES-1 +: 2*LANES],
|
924 |
|
|
dqs_pattern[5:4] };
|
925 |
18 |
dgisselq |
// Second command (of four)
|
926 |
21 |
dgisselq |
assign o_ddr_cmd_b = {cmd_b,drive_dqs[1],ddr_dm[4*LANES-1 +: 2*LANES],
|
927 |
|
|
dqs_pattern[3:2] };
|
928 |
18 |
dgisselq |
// Third command (of four)
|
929 |
21 |
dgisselq |
assign o_ddr_cmd_c = {cmd_c,drive_dqs[1],ddr_dm[2*LANES +: 2*LANES],
|
930 |
|
|
dqs_pattern[3:2] };
|
931 |
18 |
dgisselq |
// Fourth command (of four)--occupies the last timeslot
|
932 |
21 |
dgisselq |
assign o_ddr_cmd_d = {cmd_d,drive_dqs[0],ddr_dm[0*LANES +: 2*LANES],
|
933 |
|
|
dqs_pattern[1:0] };
|
934 |
2 |
dgisselq |
|
935 |
21 |
dgisselq |
initial o_wb_ack = 0;
|
936 |
|
|
always @(posedge i_clk)
|
937 |
|
|
if (i_reset || !i_wb_cyc)
|
938 |
|
|
o_wb_ack <= 0;
|
939 |
|
|
else
|
940 |
|
|
o_wb_ack <= bus_ack[BUSNOW];
|
941 |
16 |
dgisselq |
|
942 |
13 |
dgisselq |
always @(posedge i_clk)
|
943 |
7 |
dgisselq |
o_wb_data <= i_ddr_data;
|
944 |
4 |
dgisselq |
|
945 |
21 |
dgisselq |
////////////////////////////////////////////////////////////////////////////////
|
946 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
947 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
948 |
|
|
/////
|
949 |
|
|
///// Formal methods section
|
950 |
|
|
/////
|
951 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
952 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
953 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
954 |
|
|
`ifdef FORMAL
|
955 |
|
|
reg f_past_valid;
|
956 |
|
|
|
957 |
|
|
initial f_past_valid = 0;
|
958 |
|
|
always @(posedge i_clk)
|
959 |
|
|
f_past_valid <= 1;
|
960 |
|
|
|
961 |
|
|
////////////////////////////////////////////////////////////////////////
|
962 |
|
|
//
|
963 |
|
|
// Bus interface(s)
|
964 |
|
|
//
|
965 |
|
|
localparam F_LGDEPTH = 4;
|
966 |
|
|
wire [F_LGDEPTH-1:0] f_nreqs, f_nacks, f_outstanding;
|
967 |
|
|
|
968 |
|
|
localparam F_STB = 2+AW+DW+DW/8-1;
|
969 |
|
|
localparam F_PKTCOL = DW+DW/8;
|
970 |
|
|
localparam F_PKTBANK = F_PKTCOL + 10 - 3;
|
971 |
|
|
localparam F_PKTROW = F_PKTBANK + LGNBANKS;
|
972 |
|
|
reg [F_STB:0] f_rwb_packet, f_swb_packet, f_cwb_packet;
|
973 |
|
|
wire [F_STB:0] f_iwb_packet;
|
974 |
|
|
wire [LGNROWS-1:0] rwb_row, swb_row, cwb_row;
|
975 |
|
|
wire [LGNBANKS-1:0] rwb_bank, swb_bank, cwb_bank;
|
976 |
|
|
wire [9:0] rwb_col, swb_col, cwb_col;
|
977 |
|
|
wire [LGNROWS+LGNBANKS-1:0] rwb_next, swb_next;
|
978 |
|
|
(* anyconst *) reg [LGNBANKS-1:0] f_const_bank;
|
979 |
|
|
|
980 |
|
|
|
981 |
|
|
fwb_slave #(.AW(AW), .DW(DW),
|
982 |
|
|
.F_OPT_DISCONTINUOUS(1),
|
983 |
|
|
.F_OPT_RMW_BUS_OPTION(1),
|
984 |
|
|
.F_OPT_MINCLOCK_DELAY(0),
|
985 |
|
|
.F_LGDEPTH(F_LGDEPTH))
|
986 |
|
|
fwb(i_clk, i_reset,
|
987 |
|
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
|
988 |
|
|
o_wb_ack, o_wb_stall, o_wb_data, 1'b0,
|
989 |
|
|
f_nreqs, f_nacks, f_outstanding);
|
990 |
|
|
|
991 |
|
|
////////////////////////////////////////////////////////////////////////
|
992 |
|
|
//
|
993 |
|
|
//
|
994 |
|
|
// Reset Logic
|
995 |
|
|
//
|
996 |
|
|
//
|
997 |
|
|
////////////////////////////////////////////////////////////////////////
|
998 |
|
|
//
|
999 |
|
|
//
|
1000 |
|
|
//
|
1001 |
|
|
reg [4:0] f_reset_addr, f_reset_next, f_reset_active;
|
1002 |
|
|
reg [24:0] f_reset_insn, f_reset_next_insn, f_reset_active_insn;
|
1003 |
|
|
// function [24:0] get_reset_instruction;
|
1004 |
|
|
|
1005 |
|
|
always @(*)
|
1006 |
|
|
if (reset_override)
|
1007 |
|
|
assert(reset_address <= 4'hf);
|
1008 |
|
|
else
|
1009 |
|
|
assert(reset_address == 4'hf);
|
1010 |
|
|
|
1011 |
|
|
initial f_reset_addr = 5'h10;
|
1012 |
|
|
initial f_reset_next = 5'h10;
|
1013 |
|
|
initial f_reset_active = 5'h10;
|
1014 |
|
|
always @(posedge i_clk)
|
1015 |
|
|
if (i_reset)
|
1016 |
|
|
begin
|
1017 |
|
|
f_reset_addr <= 5'h10;
|
1018 |
|
|
f_reset_next <= 5'h10;
|
1019 |
|
|
f_reset_active <= 5'h10;
|
1020 |
|
|
end else if (reset_ztimer)
|
1021 |
|
|
begin
|
1022 |
|
|
if (reset_override && !reset_instruction[DDR_RSTDONE])
|
1023 |
|
|
f_reset_addr <= f_reset_addr + 1;
|
1024 |
|
|
f_reset_addr[4]<= 1'b0;
|
1025 |
|
|
|
1026 |
|
|
f_reset_next <= { 1'b0, f_reset_addr[3:0] };
|
1027 |
|
|
f_reset_active <= f_reset_next;
|
1028 |
|
|
end
|
1029 |
|
|
|
1030 |
|
|
always @(*)
|
1031 |
|
|
if (f_reset_addr == 5'h10)
|
1032 |
|
|
begin
|
1033 |
|
|
assert(f_reset_next == 5'h10);
|
1034 |
|
|
assert(f_reset_active == 5'h10);
|
1035 |
|
|
end else if (f_reset_active == 5'h10)
|
1036 |
|
|
begin
|
1037 |
|
|
assert(f_reset_addr[4:0] == 5'h1);
|
1038 |
|
|
assert(f_reset_next[4:0] == 5'h0);
|
1039 |
|
|
end else if (f_reset_active == 5'hf)
|
1040 |
|
|
begin
|
1041 |
|
|
assert(f_reset_next == 5'h0f);
|
1042 |
|
|
assert(f_reset_active == 5'h0f);
|
1043 |
|
|
end else if (f_reset_next == 5'hf)
|
1044 |
|
|
begin
|
1045 |
|
|
assert(f_reset_addr == 5'h0f);
|
1046 |
|
|
assert(f_reset_active == 5'h0e);
|
1047 |
|
|
end else
|
1048 |
|
|
begin
|
1049 |
|
|
assert(f_reset_next[3:0]+1 == f_reset_addr[3:0]);
|
1050 |
|
|
assert(f_reset_active[3:0]+1 == f_reset_next[3:0]);
|
1051 |
|
|
|
1052 |
|
|
assert(!f_reset_addr[4]);
|
1053 |
|
|
assert(!f_reset_next[4]);
|
1054 |
|
|
assert(!f_reset_active[4]);
|
1055 |
|
|
end
|
1056 |
|
|
|
1057 |
|
|
always @(*)
|
1058 |
|
|
begin
|
1059 |
|
|
assert(f_reset_addr <= 5'h10);
|
1060 |
|
|
assert(f_reset_next <= 5'h10);
|
1061 |
|
|
assert(f_reset_active <= 5'h10);
|
1062 |
|
|
end
|
1063 |
|
|
|
1064 |
|
|
always @(*)
|
1065 |
|
|
if (reset_timer != 0)
|
1066 |
|
|
assert(!reset_ztimer);
|
1067 |
|
|
else if (!reset_override)
|
1068 |
|
|
assert(reset_ztimer);
|
1069 |
|
|
|
1070 |
|
|
always @(*)
|
1071 |
|
|
if (f_reset_addr == 5'h10)
|
1072 |
|
|
f_reset_insn = INITIAL_RESET_INSTRUCTION;
|
1073 |
|
|
else
|
1074 |
|
|
f_reset_insn = get_reset_instruction(f_reset_addr[3:0]);
|
1075 |
|
|
|
1076 |
|
|
always @(*)
|
1077 |
|
|
if (f_reset_next == 5'h10)
|
1078 |
|
|
f_reset_next_insn = INITIAL_RESET_INSTRUCTION;
|
1079 |
|
|
else
|
1080 |
|
|
f_reset_next_insn = get_reset_instruction(f_reset_next[3:0]);
|
1081 |
|
|
|
1082 |
|
|
always @(*)
|
1083 |
|
|
if (f_reset_active == 5'h10)
|
1084 |
|
|
f_reset_active_insn= INITIAL_RESET_INSTRUCTION;
|
1085 |
|
|
else
|
1086 |
|
|
f_reset_active_insn= get_reset_instruction(f_reset_active[3:0]);
|
1087 |
|
|
|
1088 |
|
|
always @(*)
|
1089 |
|
|
assert(reset_instruction == f_reset_next_insn);
|
1090 |
|
|
|
1091 |
|
|
always @(*)
|
1092 |
|
|
if (f_reset_active_insn[DDR_RSTTIMER])
|
1093 |
|
|
begin
|
1094 |
|
|
assert(reset_ztimer == (reset_timer == 0));
|
1095 |
|
|
assert(reset_timer <= f_reset_active_insn[16:0]);
|
1096 |
|
|
end
|
1097 |
|
|
|
1098 |
|
|
always @(*)
|
1099 |
|
|
if (f_reset_active_insn[DDR_RSTDONE])
|
1100 |
|
|
assert(reset_override == 1'b0);
|
1101 |
|
|
|
1102 |
|
|
always @(*)
|
1103 |
|
|
if (reset_override)
|
1104 |
|
|
begin
|
1105 |
|
|
if (f_reset_next == 5'h10)
|
1106 |
|
|
assert(reset_cmd == { DDR_NOOP, f_reset_active_insn[16:0]});
|
1107 |
|
|
else
|
1108 |
|
|
assert(reset_cmd == f_reset_active_insn[20:0]);
|
1109 |
|
|
end
|
1110 |
|
|
|
1111 |
|
|
always @(posedge i_clk)
|
1112 |
|
|
if (!reset_override && $past(!reset_override))
|
1113 |
|
|
assert(reset_ztimer);
|
1114 |
|
|
|
1115 |
|
|
always @(posedge i_clk)
|
1116 |
|
|
assert(reset_address == f_reset_addr[3:0]);
|
1117 |
|
|
|
1118 |
|
|
////////////////////////////////////////////////////////////////////////
|
1119 |
|
|
//
|
1120 |
|
|
//
|
1121 |
|
|
// Refresh Logic
|
1122 |
|
|
//
|
1123 |
|
|
//
|
1124 |
|
|
////////////////////////////////////////////////////////////////////////
|
1125 |
|
|
//
|
1126 |
|
|
//
|
1127 |
|
|
//
|
1128 |
|
|
reg [3:0] f_refresh_addr, f_refresh_next, f_refresh_active;
|
1129 |
|
|
reg [24:0] f_refresh_next_insn, f_refresh_active_insn;
|
1130 |
|
|
|
1131 |
|
|
initial f_refresh_addr = 4'h8;
|
1132 |
|
|
always @(posedge i_clk)
|
1133 |
|
|
if (reset_override)
|
1134 |
|
|
// refresh_instruction <= { 4'h2, DDR_NOOP, 17'd1 };
|
1135 |
|
|
f_refresh_addr <= 4'h8;
|
1136 |
|
|
else if (refresh_ztimer)
|
1137 |
|
|
begin
|
1138 |
|
|
f_refresh_addr <= f_refresh_addr + 1;
|
1139 |
|
|
f_refresh_addr[3] <= 1'b0;
|
1140 |
|
|
end
|
1141 |
|
|
|
1142 |
|
|
initial f_refresh_next = 4'h8;
|
1143 |
|
|
always @(posedge i_clk)
|
1144 |
|
|
if (reset_override)
|
1145 |
|
|
f_refresh_next <= 4'h8;
|
1146 |
|
|
else if (refresh_ztimer)
|
1147 |
|
|
begin
|
1148 |
|
|
if (f_refresh_addr == 4'h8)
|
1149 |
|
|
f_refresh_next <= 4'h0;
|
1150 |
|
|
else
|
1151 |
|
|
f_refresh_next <= f_refresh_addr;
|
1152 |
|
|
end
|
1153 |
|
|
|
1154 |
|
|
initial f_refresh_active = 4'h8;
|
1155 |
|
|
always @(posedge i_clk)
|
1156 |
|
|
if (reset_override)
|
1157 |
|
|
f_refresh_active <= 4'h8;
|
1158 |
|
|
else if (refresh_ztimer)
|
1159 |
|
|
f_refresh_active <= f_refresh_next;
|
1160 |
|
|
|
1161 |
|
|
wire [3:0] f_refresh_next_plus_one, f_refresh_active_plus_one;
|
1162 |
|
|
assign f_refresh_next_plus_one = f_refresh_next + 1;
|
1163 |
|
|
assign f_refresh_active_plus_one = f_refresh_active + 1;
|
1164 |
|
|
|
1165 |
|
|
always @(*)
|
1166 |
|
|
begin
|
1167 |
|
|
assert(refresh_addr == f_refresh_addr[2:0]);
|
1168 |
|
|
|
1169 |
|
|
assert(f_refresh_addr <= 4'h8);
|
1170 |
|
|
assert(f_refresh_next <= 4'h8);
|
1171 |
|
|
assert(f_refresh_active <= 4'h8);
|
1172 |
|
|
|
1173 |
|
|
if (f_refresh_addr == 4'h8)
|
1174 |
|
|
begin
|
1175 |
|
|
assert(f_refresh_next == 4'h8);
|
1176 |
|
|
assert(f_refresh_active == 4'h8);
|
1177 |
|
|
end else if (f_refresh_next == 4'h8)
|
1178 |
|
|
begin
|
1179 |
|
|
assert(f_refresh_addr == 4'h1);
|
1180 |
|
|
assert(f_refresh_active == 4'h8);
|
1181 |
|
|
end else begin
|
1182 |
|
|
assert(f_refresh_addr < 4'h8);
|
1183 |
|
|
assert(f_refresh_next < 4'h8);
|
1184 |
|
|
assert(f_refresh_active <= 4'h8);
|
1185 |
|
|
if (f_refresh_next > 0)
|
1186 |
|
|
assert(!f_refresh_active[3]);
|
1187 |
|
|
|
1188 |
|
|
assert(f_refresh_next_plus_one[2:0] == f_refresh_addr[2:0]);
|
1189 |
|
|
if (f_refresh_active == 4'h8)
|
1190 |
|
|
assert(f_refresh_next[2:0] == 3'h0);
|
1191 |
|
|
else
|
1192 |
|
|
assert(f_refresh_active_plus_one[2:0] == f_refresh_next[2:0]);
|
1193 |
|
|
end
|
1194 |
|
|
end
|
1195 |
|
|
|
1196 |
|
|
always @(*)
|
1197 |
|
|
begin
|
1198 |
|
|
if (f_refresh_next == 4'h8)
|
1199 |
|
|
f_refresh_next_insn = INITIAL_REFRESH_INSTRUCTION;
|
1200 |
|
|
else
|
1201 |
|
|
f_refresh_next_insn =get_refresh_instruction(f_refresh_next[2:0]);
|
1202 |
|
|
if (f_refresh_active == 4'h8)
|
1203 |
|
|
f_refresh_active_insn = INITIAL_REFRESH_INSTRUCTION;
|
1204 |
|
|
else
|
1205 |
|
|
f_refresh_active_insn =get_refresh_instruction(f_refresh_active[2:0]);
|
1206 |
|
|
end
|
1207 |
|
|
|
1208 |
|
|
always @(*)
|
1209 |
|
|
assert(f_refresh_next_insn == refresh_instruction);
|
1210 |
|
|
|
1211 |
|
|
always @(*)
|
1212 |
|
|
if (!reset_override)
|
1213 |
|
|
assert(pre_refresh_stall == f_refresh_active_insn[DDR_PREREFRESH_STALL]);
|
1214 |
|
|
|
1215 |
|
|
always @(*)
|
1216 |
|
|
assert(need_refresh == f_refresh_active_insn[DDR_NEEDREFRESH]);
|
1217 |
|
|
|
1218 |
|
|
always @(*)
|
1219 |
|
|
if (!reset_override)
|
1220 |
|
|
begin
|
1221 |
|
|
assert(need_refresh == f_refresh_active_insn[DDR_NEEDREFRESH]);
|
1222 |
|
|
assert(pre_refresh_stall == f_refresh_active_insn[DDR_PREREFRESH_STALL]);
|
1223 |
|
|
if (f_refresh_addr == 4'h8)
|
1224 |
|
|
assert(refresh_counter <= 4);
|
1225 |
|
|
else if (f_refresh_active_insn[DDR_RFTIMER])
|
1226 |
|
|
assert(refresh_counter <= f_refresh_active_insn[16:0]);
|
1227 |
|
|
else
|
1228 |
|
|
assert(refresh_counter == 0 && refresh_ztimer);
|
1229 |
|
|
|
1230 |
|
|
assert(refresh_cmd == f_refresh_active_insn[20:0]);
|
1231 |
|
|
end
|
1232 |
|
|
|
1233 |
|
|
always @(posedge i_clk)
|
1234 |
|
|
if (f_past_valid && $past(!i_reset && reset_override))
|
1235 |
|
|
// assert(refresh_cmd == f_refresh_next_insn[20:0]);
|
1236 |
|
|
assert(refresh_cmd == INITIAL_REFRESH_INSTRUCTION[20:0]);
|
1237 |
|
|
|
1238 |
|
|
////////////////////////////////////////////////////////////////////////
|
1239 |
|
|
//
|
1240 |
|
|
// Data logic
|
1241 |
|
|
//
|
1242 |
|
|
////////////////////////////////////////////////////////////////////////
|
1243 |
|
|
//
|
1244 |
|
|
//
|
1245 |
|
|
assign f_iwb_packet = { i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel };
|
1246 |
|
|
|
1247 |
|
|
|
1248 |
|
|
always @(*)
|
1249 |
|
|
if (i_reset)
|
1250 |
|
|
assume(o_wb_stall && f_outstanding == 0);
|
1251 |
|
|
|
1252 |
|
|
else if (i_wb_cyc)
|
1253 |
|
|
assert(f_outstanding == (r_pending ? 1:0)+ (s_pending ? 1:0)
|
1254 |
|
|
+ (bus_ack[0] ? 1:0) + (bus_ack[1] ? 1:0)
|
1255 |
|
|
+ (bus_ack[2] ? 1:0)
|
1256 |
|
|
+ (o_wb_ack ? 1:0));
|
1257 |
|
|
|
1258 |
|
|
always @(*)
|
1259 |
|
|
if (reset_override)
|
1260 |
|
|
assert(f_outstanding == 0 && o_wb_stall);
|
1261 |
|
|
|
1262 |
|
|
initial f_rwb_packet = 0;
|
1263 |
|
|
always @(posedge i_clk)
|
1264 |
|
|
if (i_reset || !i_wb_cyc)
|
1265 |
|
|
f_rwb_packet <= 0;
|
1266 |
|
|
else if (!o_wb_stall)
|
1267 |
|
|
f_rwb_packet <= f_iwb_packet;
|
1268 |
|
|
else if (!pipe_stall)
|
1269 |
|
|
f_rwb_packet <= 0;
|
1270 |
|
|
|
1271 |
|
|
initial f_swb_packet = 0;
|
1272 |
|
|
always @(posedge i_clk)
|
1273 |
|
|
if (i_reset || !i_wb_cyc)
|
1274 |
|
|
f_swb_packet <= 0;
|
1275 |
|
|
else if (!pipe_stall)
|
1276 |
|
|
f_swb_packet <= f_rwb_packet;
|
1277 |
|
|
|
1278 |
|
|
initial f_cwb_packet = 0;
|
1279 |
|
|
always @(posedge i_clk)
|
1280 |
|
|
if (i_reset || !i_wb_cyc)
|
1281 |
|
|
f_cwb_packet <= 0;
|
1282 |
|
|
else if (!pipe_stall)
|
1283 |
|
|
f_cwb_packet <= f_swb_packet;
|
1284 |
|
|
else
|
1285 |
|
|
f_cwb_packet <= 0;
|
1286 |
|
|
|
1287 |
|
|
//
|
1288 |
|
|
// Make sure the packet contents are what they should be
|
1289 |
|
|
//
|
1290 |
|
|
|
1291 |
|
|
assign rwb_row = f_rwb_packet[F_STB-2:F_PKTROW];
|
1292 |
|
|
assign rwb_bank = f_rwb_packet[F_PKTROW-1 :F_PKTBANK];
|
1293 |
|
|
assign rwb_col = { f_rwb_packet[F_PKTBANK-1:F_PKTCOL], 3'h0 };
|
1294 |
|
|
assign rwb_next = { rwb_row, rwb_bank }+1;
|
1295 |
|
|
always @(*)
|
1296 |
|
|
if (f_rwb_packet[F_STB])
|
1297 |
|
|
begin
|
1298 |
|
|
assert(r_pending);
|
1299 |
|
|
assert(r_we == f_rwb_packet[F_STB-1]);
|
1300 |
|
|
assert(r_row == rwb_row);
|
1301 |
|
|
assert(r_bank == rwb_bank);
|
1302 |
|
|
assert(r_col == rwb_col);
|
1303 |
|
|
assert(r_data == f_rwb_packet[DW+DW/8-1:DW/8]);
|
1304 |
|
|
assert(r_sel == f_rwb_packet[DW/8-1:0]);
|
1305 |
|
|
|
1306 |
|
|
assert({ r_nxt_row, r_nxt_bank } == rwb_next);
|
1307 |
|
|
end else
|
1308 |
|
|
assert(!r_pending);
|
1309 |
|
|
|
1310 |
|
|
assign swb_row = f_swb_packet[F_STB-2:F_PKTROW];
|
1311 |
|
|
assign swb_bank = f_swb_packet[F_PKTROW-1 :F_PKTBANK];
|
1312 |
|
|
assign swb_col = { f_swb_packet[F_PKTBANK-1:F_PKTCOL], 3'h0 };
|
1313 |
|
|
assign swb_next = { swb_row, swb_bank }+1;
|
1314 |
|
|
always @(*)
|
1315 |
|
|
if (f_swb_packet[F_STB])
|
1316 |
|
|
begin
|
1317 |
|
|
assert(s_pending);
|
1318 |
|
|
assert(f_swb_packet[F_STB-1] == s_we);
|
1319 |
|
|
assert(s_row == swb_row);
|
1320 |
|
|
assert(s_bank == swb_bank);
|
1321 |
|
|
assert(s_col == swb_col);
|
1322 |
|
|
assert(f_swb_packet[DW+DW/8-1:DW/8] == { s_data});
|
1323 |
|
|
if (f_swb_packet[F_STB-1])
|
1324 |
|
|
assert(f_swb_packet[DW/8-1:0] == ~s_sel);
|
1325 |
|
|
else
|
1326 |
|
|
assert(s_sel == 0);
|
1327 |
|
|
assert(cmd_pipe != 0);
|
1328 |
|
|
|
1329 |
|
|
assert({ s_nxt_row, s_nxt_bank } == swb_next);
|
1330 |
|
|
end else
|
1331 |
|
|
assert(!s_pending);
|
1332 |
|
|
|
1333 |
|
|
assign cwb_row = f_cwb_packet[F_STB-2:F_PKTROW];
|
1334 |
|
|
assign cwb_bank = f_cwb_packet[F_PKTROW-1 :F_PKTBANK];
|
1335 |
|
|
assign cwb_col = { f_cwb_packet[F_PKTBANK-1:F_PKTCOL], 3'h0 };
|
1336 |
|
|
always @(*)
|
1337 |
|
|
if (f_cwb_packet[F_STB])
|
1338 |
|
|
begin
|
1339 |
|
|
if (f_cwb_packet[F_STB-1])
|
1340 |
|
|
begin
|
1341 |
|
|
// A write command
|
1342 |
|
|
assert(cmd_d[DDR_CSBIT:DDR_WEBIT] == DDR_WRITE);
|
1343 |
|
|
assert(bus_ack[0] == 1);
|
1344 |
|
|
assert(bus_read[0] == 0);
|
1345 |
|
|
assert(bus_fifo_sel[0] == (~f_cwb_packet[0 +: DW/8]));
|
1346 |
|
|
assert(bus_fifo_data[0] == f_cwb_packet[DW/8 +: DW]);
|
1347 |
|
|
end else begin
|
1348 |
|
|
// A read command
|
1349 |
|
|
assert(cmd_d[DDR_CSBIT:DDR_WEBIT] == DDR_READ);
|
1350 |
|
|
//
|
1351 |
|
|
assert(bus_ack[0] == 1);
|
1352 |
|
|
assert(bus_read[0] == 1);
|
1353 |
|
|
end
|
1354 |
|
|
|
1355 |
|
|
assert(bus_active[0]);
|
1356 |
|
|
|
1357 |
|
|
assert(!cmd_d[DDR_CSBIT]);
|
1358 |
|
|
assert(bank_status[cwb_bank] || need_refresh);
|
1359 |
|
|
assert(bank_address[cwb_bank] == cwb_row);
|
1360 |
|
|
|
1361 |
|
|
assert(cmd_d[DDR_WEBIT-1:0] ==
|
1362 |
|
|
{cwb_bank, 3'h0, 1'b0, cwb_col });
|
1363 |
|
|
|
1364 |
|
|
assert((cmd_b[DDR_CSBIT:DDR_WEBIT] != DDR_PRECHARGE)
|
1365 |
|
|
|| (cmd_b[DDR_WEBIT-1:DDR_WEBIT-LGNBANKS] != cwb_bank));
|
1366 |
|
|
end else if (f_past_valid)
|
1367 |
|
|
begin
|
1368 |
|
|
assert(cmd_d[DDR_CSBIT]);
|
1369 |
|
|
end
|
1370 |
|
|
|
1371 |
|
|
always @(posedge i_clk)
|
1372 |
|
|
if (f_past_valid && $past(bus_ack[BUSREG]))
|
1373 |
|
|
assert(ddr_dm == bus_fifo_sel[BUSNOW]);
|
1374 |
|
|
else if (f_past_valid && $past(!bus_read[BUSREG]))
|
1375 |
|
|
assert(&ddr_dm);
|
1376 |
|
|
|
1377 |
|
|
always @(*)
|
1378 |
|
|
if (!r_pending && !s_pending)
|
1379 |
|
|
begin
|
1380 |
|
|
assert(cmd_pipe == 0);
|
1381 |
|
|
// assert(nxt_pipe == 0);
|
1382 |
|
|
end
|
1383 |
|
|
|
1384 |
|
|
always @(posedge i_clk)
|
1385 |
|
|
if (f_past_valid && !$past(i_reset))
|
1386 |
|
|
begin
|
1387 |
|
|
if ($past(f_cwb_packet[F_STB:F_STB-1] == 2'b11))
|
1388 |
|
|
// Following a write
|
1389 |
|
|
assert(drive_dqs[0]);
|
1390 |
|
|
else if ($past(f_cwb_packet[F_STB:F_STB-1] == 2'b10))
|
1391 |
|
|
// Following a read
|
1392 |
|
|
assert(drive_dqs[1:0] == 2'b00);
|
1393 |
|
|
end
|
1394 |
|
|
|
1395 |
|
|
always @(*)
|
1396 |
|
|
assert(dir_stall == (r_pending && s_pending && r_we != s_we));
|
1397 |
|
|
|
1398 |
|
|
////////////////////////////////////////////////////////////////////////
|
1399 |
|
|
//
|
1400 |
|
|
//
|
1401 |
|
|
always @(posedge i_clk)
|
1402 |
|
|
if (f_past_valid && $past(bank_status[f_const_bank] != 0))
|
1403 |
|
|
begin
|
1404 |
|
|
// Can't re-activate an active bank
|
1405 |
|
|
assert((cmd_b[DDR_CSBIT:DDR_WEBIT] != DDR_ACTIVATE)
|
1406 |
|
|
||(cmd_b[DDR_WEBIT-1:DDR_WEBIT-LGNBANKS] != f_const_bank));
|
1407 |
|
|
assert((cmd_c[DDR_CSBIT:DDR_WEBIT] != DDR_ACTIVATE)
|
1408 |
|
|
||(cmd_c[DDR_WEBIT-1:DDR_WEBIT-LGNBANKS] != f_const_bank));
|
1409 |
|
|
assert((cmd_d[DDR_CSBIT:DDR_WEBIT] != DDR_ACTIVATE)
|
1410 |
|
|
||(cmd_d[DDR_WEBIT-1:DDR_WEBIT-LGNBANKS] != f_const_bank));
|
1411 |
|
|
end
|
1412 |
|
|
|
1413 |
|
|
always @(posedge i_clk)
|
1414 |
|
|
// if (f_past_valid && !(&bank_status[f_const_bank]))
|
1415 |
|
|
if (f_past_valid && $past(!bank_status[f_const_bank]))
|
1416 |
|
|
begin
|
1417 |
|
|
// Can't de-activate an inactive bank
|
1418 |
|
|
assert((cmd_b[DDR_CSBIT:DDR_WEBIT] != DDR_PRECHARGE)
|
1419 |
|
|
||(cmd_b[DDR_WEBIT-1:DDR_WEBIT-LGNBANKS] !=f_const_bank));
|
1420 |
|
|
assert((cmd_c[DDR_CSBIT:DDR_WEBIT] != DDR_PRECHARGE)
|
1421 |
|
|
||(cmd_c[DDR_WEBIT-1:DDR_WEBIT-LGNBANKS] !=f_const_bank));
|
1422 |
|
|
assert((cmd_d[DDR_CSBIT:DDR_WEBIT] != DDR_PRECHARGE)
|
1423 |
|
|
||(cmd_d[DDR_WEBIT-1:DDR_WEBIT-LGNBANKS] !=f_const_bank));
|
1424 |
|
|
|
1425 |
|
|
if (!need_refresh)
|
1426 |
|
|
// Can't read or write from a inactive bank
|
1427 |
|
|
assert(((cmd_d[DDR_CSBIT:DDR_WEBIT] != DDR_WRITE)
|
1428 |
|
|
&&(cmd_d[DDR_CSBIT:DDR_WEBIT] != DDR_READ))
|
1429 |
|
|
||(cmd_d[DDR_WEBIT-1:DDR_WEBIT-LGNBANKS] !=f_const_bank));
|
1430 |
|
|
end
|
1431 |
|
|
|
1432 |
|
|
always @(*)
|
1433 |
|
|
if (need_refresh && !cmd_a[DDR_CSBIT]
|
1434 |
|
|
&& (cmd_a[DDR_CSBIT:DDR_WEBIT] != DDR_NOOP))
|
1435 |
|
|
begin
|
1436 |
|
|
assert(!r_pending);
|
1437 |
|
|
assert(!s_pending);
|
1438 |
|
|
assert(cmd_b[DDR_CSBIT]);
|
1439 |
|
|
assert(cmd_c[DDR_CSBIT]);
|
1440 |
|
|
if (cmd_a[DDR_CSBIT:DDR_WEBIT] != DDR_PRECHARGE)
|
1441 |
|
|
assert(cmd_d[DDR_CSBIT]);
|
1442 |
|
|
end
|
1443 |
|
|
|
1444 |
|
|
////////////////////////////////////////////////////////////////////////
|
1445 |
|
|
//
|
1446 |
|
|
//
|
1447 |
|
|
always @(*)
|
1448 |
|
|
if (pipe_stall && r_pending)
|
1449 |
|
|
assert(o_wb_stall);
|
1450 |
|
|
|
1451 |
|
|
always @(*)
|
1452 |
|
|
assert(pipe_stall == (|cmd_pipe[1:0]));
|
1453 |
|
|
|
1454 |
|
|
|
1455 |
|
|
always @(*)
|
1456 |
|
|
assert(refresh_ztimer == (refresh_counter == 0));
|
1457 |
|
|
|
1458 |
|
|
always @(*)
|
1459 |
|
|
casez(cmd_pipe)
|
1460 |
|
|
3'b000: begin end
|
1461 |
|
|
3'b001: begin end
|
1462 |
|
|
3'b010: begin end
|
1463 |
|
|
3'b100: begin end
|
1464 |
|
|
default: assert(0);
|
1465 |
|
|
endcase
|
1466 |
|
|
|
1467 |
|
|
always @(*)
|
1468 |
|
|
casez({ drive_dqs, dqs_pattern })
|
1469 |
|
|
// These are the good patterns
|
1470 |
|
|
// In their proper progression
|
1471 |
|
|
{ 3'b001, 6'b????00 }: begin end
|
1472 |
|
|
{ 3'b111, 6'b101010 }: begin end
|
1473 |
|
|
{ 3'b100, 6'b11???? }: begin end
|
1474 |
|
|
// It is possible to have an empty
|
1475 |
|
|
// cycle between write cycles, then
|
1476 |
|
|
// you'd have a drive_dqs of 101
|
1477 |
|
|
{ 3'b101, 6'b11??00 }: begin end
|
1478 |
|
|
// Don't care, 'cause nothing's driven
|
1479 |
|
|
{ 3'b000, 6'b?????? }: begin end
|
1480 |
|
|
// Everything else is disallowed
|
1481 |
|
|
default: assert(0);
|
1482 |
|
|
endcase
|
1483 |
|
|
|
1484 |
|
|
always @(posedge i_clk)
|
1485 |
|
|
if (f_past_valid && $past(drive_dqs == 3'b001))
|
1486 |
|
|
assert(drive_dqs == 3'b111);
|
1487 |
|
|
|
1488 |
|
|
always @(posedge i_clk)
|
1489 |
|
|
if (f_past_valid && $past(drive_dqs == 3'b111))
|
1490 |
|
|
assert(drive_dqs[2]);
|
1491 |
|
|
|
1492 |
|
|
////////////////////////////////////////////////////////////////////////
|
1493 |
|
|
//
|
1494 |
|
|
// (Careless) problem limiting assumption section
|
1495 |
|
|
//
|
1496 |
|
|
////////////////////////////////////////////////////////////////////////
|
1497 |
|
|
//
|
1498 |
|
|
//
|
1499 |
|
|
`endif
|
1500 |
2 |
dgisselq |
endmodule
|