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dgisselq |
`timescale 1 ns / 1 ps
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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: axi4lscope.v
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//
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dgisselq |
// Project: WBScope, a wishbone hosted scope
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dgisselq |
//
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// Purpose: This is a generic/library routine for providing a bus accessed
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// 'scope' or (perhaps more appropriately) a bus accessed logic analyzer.
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// The general operation is such that this 'scope' can record and report
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// on any 32 bit value transiting through the FPGA. Once started and
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// reset, the scope records a copy of the input data every time the clock
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// ticks with the circuit enabled. That is, it records these values up
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// until the trigger. Once the trigger goes high, the scope will record
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dgisselq |
// for br_holdoff more counts before stopping. Values may then be read
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dgisselq |
// from the buffer, oldest to most recent. After reading, the scope may
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// then be reset for another run.
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//
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// In general, therefore, operation happens in this fashion:
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// 1. A reset is issued.
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// 2. Recording starts, in a circular buffer, and continues until
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// 3. The trigger line is asserted.
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// The scope registers the asserted trigger by setting
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// the 'o_triggered' output flag.
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// 4. A counter then ticks until the last value is written
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// The scope registers that it has stopped recording by
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// setting the 'o_stopped' output flag.
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// 5. The scope recording is then paused until the next reset.
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// 6. While stopped, the CPU can read the data from the scope
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// 7. -- oldest to most recent
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// 8. -- one value per i_rd&i_data_clk
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// 9. Writes to the data register reset the address to the
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// beginning of the buffer
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//
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// Although the data width DW is parameterized, it is not very changable,
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// since the width is tied to the width of the data bus, as is the
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// control word. Therefore changing the data width would require changing
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// the interface. It's doable, but it would be a change to the interface.
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//
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// The SYNCHRONOUS parameter turns on and off meta-stability
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// synchronization. Ideally a wishbone scope able to handle one or two
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// clocks would have a changing number of ports as this SYNCHRONOUS
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// parameter changed. Other than running another script to modify
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// this, I don't know how to do that so ... we'll just leave it running
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// off of two clocks or not.
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//
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//
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// Internal to this routine, registers and wires are named with one of the
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// following prefixes:
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//
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// i_ An input port to the routine
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// o_ An output port of the routine
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// br_ A register, controlled by the bus clock
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// dr_ A register, controlled by the data clock
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// bw_ A wire/net, controlled by the bus clock
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// dw_ A wire/net, controlled by the data clock
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//
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// And, of course, since AXI wants to be particular about their port
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// naming conventions, anything beginning with
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//
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// S_AXI_
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//
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// is a signal associated with this function as an AXI slave.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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dgisselq |
// Copyright (C) 2015-2018, Gisselquist Technology, LLC
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dgisselq |
//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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dgisselq |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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dgisselq |
`default_nettype none
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//
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dgisselq |
module axi4lscope
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#(
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// Users to add parameters here
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parameter [4:0] LGMEM = 5'd10,
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parameter BUSW = 32,
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parameter SYNCHRONOUS=1,
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dgisselq |
parameter HOLDOFFBITS = 20,
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parameter [(HOLDOFFBITS-1):0] DEFAULT_HOLDOFF
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= ((1<<(LGMEM-1))-4),
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dgisselq |
// User parameters ends
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// DO NOT EDIT BELOW THIS LINE ---------------------
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// Do not modify the parameters beyond this line
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// Width of S_AXI data bus
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parameter integer C_S_AXI_DATA_WIDTH = 32,
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// Width of S_AXI address bus
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parameter integer C_S_AXI_ADDR_WIDTH = 4
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)
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(
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// Users to add ports here
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dgisselq |
input wire i_data_clk, // The data clock, can be set to ACLK
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input wire i_ce, // = '1' when recordable data is present
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input wire i_trigger,// = '1' when interesting event hapns
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input wire [31:0] i_data,
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output wire o_interrupt, // ='1' when scope has stopped
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// User ports ends
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// DO NOT EDIT BELOW THIS LINE ---------------------
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// Do not modify the ports beyond this line
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// Global Clock Signal
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input wire S_AXI_ACLK,
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// Global Reset Signal. This Signal is Active LOW
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input wire S_AXI_ARESETN,
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// Write address (issued by master, acceped by Slave)
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input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
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// Write channel Protection type. This signal indicates the
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// privilege and security level of the transaction, and whether
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// the transaction is a data access or an instruction access.
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input wire [2 : 0] S_AXI_AWPROT,
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// Write address valid. This signal indicates that the master
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// signaling valid write address and control information.
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input wire S_AXI_AWVALID,
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// Write address ready. This signal indicates that the slave
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// is ready to accept an address and associated control signals.
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output wire S_AXI_AWREADY,
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// Write data (issued by master, acceped by Slave)
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input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
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// Write strobes. This signal indicates which byte lanes hold
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// valid data. There is one write strobe bit for each eight
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// bits of the write data bus.
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input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
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// Write valid. This signal indicates that valid write
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// data and strobes are available.
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input wire S_AXI_WVALID,
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// Write ready. This signal indicates that the slave
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// can accept the write data.
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output wire S_AXI_WREADY,
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// Write response. This signal indicates the status
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// of the write transaction.
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output wire [1 : 0] S_AXI_BRESP,
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// Write response valid. This signal indicates that the channel
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// is signaling a valid write response.
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output wire S_AXI_BVALID,
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// Response ready. This signal indicates that the master
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// can accept a write response.
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input wire S_AXI_BREADY,
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// Read address (issued by master, acceped by Slave)
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input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
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// Protection type. This signal indicates the privilege
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// and security level of the transaction, and whether the
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// transaction is a data access or an instruction access.
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input wire [2 : 0] S_AXI_ARPROT,
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// Read address valid. This signal indicates that the channel
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// is signaling valid read address and control information.
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input wire S_AXI_ARVALID,
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// Read address ready. This signal indicates that the slave is
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// ready to accept an address and associated control signals.
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output wire S_AXI_ARREADY,
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// Read data (issued by slave)
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output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
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// Read response. This signal indicates the status of the
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// read transfer.
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output wire [1 : 0] S_AXI_RRESP,
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// Read valid. This signal indicates that the channel is
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// signaling the required read data.
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output wire S_AXI_RVALID,
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// Read ready. This signal indicates that the master can
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// accept the read data and response information.
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input wire S_AXI_RREADY
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// DO NOT EDIT ABOVE THIS LINE ---------------------
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);
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// AXI4LITE signals
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
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reg axi_awready;
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// reg [1 : 0] axi_bresp;
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reg axi_bvalid;
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
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reg axi_arready;
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// reg [1 : 0] axi_rresp;
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dgisselq |
wire write_stb;
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dgisselq |
///////////////////////////////////////////////////
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//
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// Decode and handle the AXI/Bus signaling
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//
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///////////////////////////////////////////////////
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//
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// Sadly, the AXI bus is *way* more complicated to
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// deal with than it needs to be. Still, we offer
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// the following as a simple means of dealing with
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// it. The majority of the code in this section
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// comes directly from a Xilinx/Vivado generated
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// file.
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//
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// Gisselquist Technology, LLC, claims no copyright
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// or ownership of this section of the code.
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//
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dgisselq |
wire i_reset, axi_bstall, axi_rstall;
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dgisselq |
assign i_reset = !S_AXI_ARESETN;
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dgisselq |
always @(*)
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if ((!axi_bstall)&&(S_AXI_AWVALID)&&(S_AXI_WVALID))
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axi_awready <= 1'b1;
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else
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axi_awready <= 1'b0;
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dgisselq |
assign S_AXI_AWREADY = axi_awready;
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dgisselq |
assign S_AXI_WREADY = axi_awready;
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dgisselq |
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always @(posedge S_AXI_ACLK)
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dgisselq |
if ((S_AXI_AWVALID)&&(S_AXI_AWREADY))
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axi_awaddr <= S_AXI_AWADDR;
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dgisselq |
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dgisselq |
initial axi_bvalid = 0;
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dgisselq |
always @(posedge S_AXI_ACLK)
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dgisselq |
if (i_reset)
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axi_bvalid <= 0;
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else if (write_stb)
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axi_bvalid <= 1'b1;
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else if (S_AXI_BREADY)
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axi_bvalid <= 1'b0;
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dgisselq |
assign S_AXI_BRESP = 2'b00; // An 'OKAY' response
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assign S_AXI_BVALID= axi_bvalid;
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dgisselq |
assign axi_bstall = (S_AXI_BVALID)&&(!S_AXI_BREADY);
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dgisselq |
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dgisselq |
always @(*)
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if (i_reset)
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axi_arready = 1'b0;
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else if (axi_rstall)
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axi_arready = 1'b0;
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else
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axi_arready = 1'b1;
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dgisselq |
always @(posedge S_AXI_ACLK)
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dgisselq |
if (i_reset)
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axi_araddr <= 0;
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else if ((axi_arready)&&(S_AXI_ARVALID))
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axi_araddr <= S_AXI_ARADDR;
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dgisselq |
assign S_AXI_ARREADY = axi_arready;
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dgisselq |
reg [1:0] rvalid;
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initial rvalid = 2'b00;
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dgisselq |
always @(posedge S_AXI_ACLK)
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dgisselq |
if (i_reset)
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rvalid <= 2'b00;
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else if ((axi_arready)&&(S_AXI_ARVALID))
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rvalid <= 2'b01;
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else if (rvalid == 2'b01)
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rvalid <= 2'b10;
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else if (S_AXI_RREADY)
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rvalid <= 2'b00;
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assign S_AXI_RVALID = rvalid[1];
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dgisselq |
assign S_AXI_RRESP = 2'b00;
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dgisselq |
assign axi_rstall = ((rvalid[0])||(S_AXI_RVALID)&&(!S_AXI_RREADY));
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dgisselq |
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///////////////////////////////////////////////////
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//
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// Final simplification of the AXI code
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//
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///////////////////////////////////////////////////
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//
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// Now that we've provided all of the bus signaling
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// above, can we make any sense of it?
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//
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// The following wires are here to provide some
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// simplification of the complex bus protocol. In
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// particular, are we reading or writing during this
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// clock? The two *should* be mutually exclusive
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// (i.e., you *shouldn't* be able to both read and
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// write on the same clock) ... but Xilinx's default
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// implementation does nothing to ensure that this
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// would be the case.
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//
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// From here on down, Gisselquist Technology, LLC,
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// claims a copyright on the code.
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//
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dgisselq |
wire bus_clock;
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assign bus_clock = S_AXI_ACLK;
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dgisselq |
wire read_from_data;
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assign read_from_data = (S_AXI_ARVALID)&&(S_AXI_ARREADY)
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&&(axi_araddr[0]);
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assign write_stb = ((axi_awready)&&(S_AXI_AWVALID)
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dgisselq |
&&(S_AXI_WVALID));
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dgisselq |
wire write_to_control;
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assign write_to_control = (write_stb)&&(!axi_awaddr[0]);
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dgisselq |
reg read_address;
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always @(posedge bus_clock)
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dgisselq |
if ((axi_arready)&&(S_AXI_ARVALID))
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dgisselq |
read_address <= axi_araddr[0];
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dgisselq |
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wire [31:0] i_wb_data;
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assign i_wb_data = S_AXI_WDATA;
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///////////////////////////////////////////////////
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//
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// The actual SCOPE
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//
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///////////////////////////////////////////////////
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//
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|
|
// Now that we've finished reading/writing from the
|
328 |
|
|
// bus, ... or at least acknowledging reads and
|
329 |
|
|
// writes from and to the bus--even if they haven't
|
330 |
|
|
// happened yet, now we implement our actual scope.
|
331 |
|
|
// This includes implementing the actual reads/writes
|
332 |
|
|
// from/to the bus.
|
333 |
|
|
//
|
334 |
|
|
// From here on down, is the heart of the scope itself.
|
335 |
|
|
//
|
336 |
|
|
reg [(LGMEM-1):0] raddr;
|
337 |
|
|
reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)];
|
338 |
|
|
|
339 |
|
|
// Our status/config register
|
340 |
|
|
wire bw_reset_request, bw_manual_trigger,
|
341 |
|
|
bw_disable_trigger, bw_reset_complete;
|
342 |
13 |
dgisselq |
reg [2:0] br_config;
|
343 |
|
|
reg [(HOLDOFFBITS-1):0] br_holdoff;
|
344 |
|
|
initial br_config = 3'b0;
|
345 |
|
|
initial br_holdoff = DEFAULT_HOLDOFF;
|
346 |
|
|
always @(posedge bus_clock)
|
347 |
14 |
dgisselq |
if (write_to_control)
|
348 |
|
|
begin
|
349 |
|
|
br_config <= { i_wb_data[31],
|
350 |
|
|
i_wb_data[27],
|
351 |
|
|
i_wb_data[26] };
|
352 |
|
|
br_holdoff <= i_wb_data[(HOLDOFFBITS-1):0];
|
353 |
|
|
end else if (bw_reset_complete)
|
354 |
|
|
br_config[2] <= 1'b1;
|
355 |
13 |
dgisselq |
assign bw_reset_request = (!br_config[2]);
|
356 |
|
|
assign bw_manual_trigger = (br_config[1]);
|
357 |
|
|
assign bw_disable_trigger = (br_config[0]);
|
358 |
12 |
dgisselq |
|
359 |
|
|
wire dw_reset, dw_manual_trigger, dw_disable_trigger;
|
360 |
|
|
generate
|
361 |
|
|
if (SYNCHRONOUS > 0)
|
362 |
|
|
begin
|
363 |
|
|
assign dw_reset = bw_reset_request;
|
364 |
|
|
assign dw_manual_trigger = bw_manual_trigger;
|
365 |
|
|
assign dw_disable_trigger = bw_disable_trigger;
|
366 |
|
|
assign bw_reset_complete = bw_reset_request;
|
367 |
|
|
end else begin
|
368 |
|
|
reg r_reset_complete;
|
369 |
|
|
(* ASYNC_REG = "TRUE" *) reg [2:0] q_iflags;
|
370 |
|
|
reg [2:0] r_iflags;
|
371 |
|
|
|
372 |
|
|
// Resets are synchronous to the bus clock, not the data clock
|
373 |
|
|
// so do a clock transfer here
|
374 |
14 |
dgisselq |
initial { q_iflags, r_iflags } = 6'h0;
|
375 |
12 |
dgisselq |
initial r_reset_complete = 1'b0;
|
376 |
13 |
dgisselq |
always @(posedge i_data_clk)
|
377 |
12 |
dgisselq |
begin
|
378 |
|
|
q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger };
|
379 |
|
|
r_iflags <= q_iflags;
|
380 |
|
|
r_reset_complete <= (dw_reset);
|
381 |
|
|
end
|
382 |
|
|
|
383 |
|
|
assign dw_reset = r_iflags[2];
|
384 |
|
|
assign dw_manual_trigger = r_iflags[1];
|
385 |
|
|
assign dw_disable_trigger = r_iflags[0];
|
386 |
|
|
|
387 |
|
|
(* ASYNC_REG = "TRUE" *) reg q_reset_complete;
|
388 |
|
|
reg qq_reset_complete;
|
389 |
|
|
// Pass an acknowledgement back from the data clock to the bus
|
390 |
|
|
// clock that the reset has been accomplished
|
391 |
|
|
initial q_reset_complete = 1'b0;
|
392 |
|
|
initial qq_reset_complete = 1'b0;
|
393 |
13 |
dgisselq |
always @(posedge bus_clock)
|
394 |
12 |
dgisselq |
begin
|
395 |
|
|
q_reset_complete <= r_reset_complete;
|
396 |
|
|
qq_reset_complete <= q_reset_complete;
|
397 |
|
|
end
|
398 |
|
|
|
399 |
|
|
assign bw_reset_complete = qq_reset_complete;
|
400 |
14 |
dgisselq |
|
401 |
|
|
`ifdef FORMAL
|
402 |
|
|
always @($global_clock)
|
403 |
|
|
if (f_past_valid_data)
|
404 |
|
|
begin
|
405 |
|
|
if ($rose(r_reset_complete))
|
406 |
|
|
assert(bw_reset_request);
|
407 |
|
|
end
|
408 |
|
|
`endif
|
409 |
12 |
dgisselq |
end endgenerate
|
410 |
|
|
|
411 |
|
|
//
|
412 |
|
|
// Set up the trigger
|
413 |
|
|
//
|
414 |
|
|
//
|
415 |
|
|
// Write with the i-clk, or input clock. All outputs read with the
|
416 |
13 |
dgisselq |
// bus clock, or bus_clock as we've called it here.
|
417 |
12 |
dgisselq |
reg dr_triggered, dr_primed;
|
418 |
|
|
wire dw_trigger;
|
419 |
|
|
assign dw_trigger = (dr_primed)&&(
|
420 |
13 |
dgisselq |
((i_trigger)&&(!dw_disable_trigger))
|
421 |
12 |
dgisselq |
||(dw_manual_trigger));
|
422 |
|
|
initial dr_triggered = 1'b0;
|
423 |
13 |
dgisselq |
always @(posedge i_data_clk)
|
424 |
14 |
dgisselq |
if (dw_reset)
|
425 |
|
|
dr_triggered <= 1'b0;
|
426 |
|
|
else if ((i_ce)&&(dw_trigger))
|
427 |
|
|
dr_triggered <= 1'b1;
|
428 |
12 |
dgisselq |
|
429 |
|
|
//
|
430 |
|
|
// Determine when memory is full and capture is complete
|
431 |
|
|
//
|
432 |
|
|
// Writes take place on the data clock
|
433 |
13 |
dgisselq |
// The counter is unsigned
|
434 |
|
|
(* ASYNC_REG="TRUE" *) reg [(HOLDOFFBITS-1):0] counter;
|
435 |
|
|
|
436 |
12 |
dgisselq |
reg dr_stopped;
|
437 |
|
|
initial dr_stopped = 1'b0;
|
438 |
13 |
dgisselq |
initial counter = 0;
|
439 |
|
|
always @(posedge i_data_clk)
|
440 |
14 |
dgisselq |
if (dw_reset)
|
441 |
|
|
counter <= 0;
|
442 |
|
|
else if ((i_ce)&&(dr_triggered)&&(!dr_stopped))
|
443 |
|
|
counter <= counter + 1'b1;
|
444 |
|
|
|
445 |
13 |
dgisselq |
always @(posedge i_data_clk)
|
446 |
14 |
dgisselq |
if ((!dr_triggered)||(dw_reset))
|
447 |
|
|
dr_stopped <= 1'b0;
|
448 |
|
|
else if (HOLDOFFBITS > 1) // if (i_ce)
|
449 |
|
|
dr_stopped <= (counter >= br_holdoff);
|
450 |
|
|
else if (HOLDOFFBITS <= 1)
|
451 |
|
|
dr_stopped <= ((i_ce)&&(dw_trigger));
|
452 |
12 |
dgisselq |
|
453 |
|
|
//
|
454 |
|
|
// Actually do our writes to memory. Record, via 'primed' when
|
455 |
|
|
// the memory is full.
|
456 |
|
|
//
|
457 |
|
|
// The 'waddr' address that we are using really crosses two clock
|
458 |
|
|
// domains. While writing and changing, it's in the data clock
|
459 |
|
|
// domain. Once stopped, it becomes part of the bus clock domain.
|
460 |
|
|
// The clock transfer on the stopped line handles the clock
|
461 |
|
|
// transfer for these signals.
|
462 |
|
|
//
|
463 |
|
|
reg [(LGMEM-1):0] waddr;
|
464 |
|
|
initial waddr = {(LGMEM){1'b0}};
|
465 |
|
|
initial dr_primed = 1'b0;
|
466 |
13 |
dgisselq |
always @(posedge i_data_clk)
|
467 |
14 |
dgisselq |
if (dw_reset) // For simulation purposes, supply a valid value
|
468 |
|
|
begin
|
469 |
|
|
waddr <= 0; // upon reset.
|
470 |
|
|
dr_primed <= 1'b0;
|
471 |
|
|
end else if ((i_ce)&&(!dr_stopped))
|
472 |
|
|
begin
|
473 |
|
|
// mem[waddr] <= i_data;
|
474 |
|
|
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
|
475 |
|
|
if (!dr_primed)
|
476 |
12 |
dgisselq |
begin
|
477 |
14 |
dgisselq |
//if (br_holdoff[(HOLDOFFBITS-1):LGMEM]==0)
|
478 |
|
|
// dr_primed <= (waddr >= br_holdoff[(LGMEM-1):0]);
|
479 |
|
|
// else
|
480 |
|
|
|
481 |
|
|
dr_primed <= (&waddr);
|
482 |
12 |
dgisselq |
end
|
483 |
14 |
dgisselq |
end
|
484 |
12 |
dgisselq |
|
485 |
13 |
dgisselq |
// Delay the incoming data so that we can get our trigger
|
486 |
|
|
// logic to line up with the data. The goal is to have a
|
487 |
|
|
// hold off of zero place the trigger in the last memory
|
488 |
|
|
// address.
|
489 |
|
|
localparam STOPDELAY = 1;
|
490 |
|
|
wire [(BUSW-1):0] wr_piped_data;
|
491 |
|
|
generate
|
492 |
|
|
if (STOPDELAY == 0)
|
493 |
|
|
// No delay ... just assign the wires to our input lines
|
494 |
|
|
assign wr_piped_data = i_data;
|
495 |
|
|
else if (STOPDELAY == 1)
|
496 |
|
|
begin
|
497 |
|
|
//
|
498 |
|
|
// Delay by one means just register this once
|
499 |
|
|
reg [(BUSW-1):0] data_pipe;
|
500 |
|
|
always @(posedge i_data_clk)
|
501 |
|
|
if (i_ce)
|
502 |
|
|
data_pipe <= i_data;
|
503 |
|
|
assign wr_piped_data = data_pipe;
|
504 |
|
|
end else begin
|
505 |
|
|
// Arbitrary delay ... use a longer pipe
|
506 |
|
|
reg [(STOPDELAY*BUSW-1):0] data_pipe;
|
507 |
|
|
|
508 |
|
|
always @(posedge i_data_clk)
|
509 |
|
|
if (i_ce)
|
510 |
|
|
data_pipe <= { data_pipe[((STOPDELAY-1)*BUSW-1):0], i_data };
|
511 |
|
|
assign wr_piped_data = { data_pipe[(STOPDELAY*BUSW-1):((STOPDELAY-1)*BUSW)] };
|
512 |
|
|
end endgenerate
|
513 |
|
|
|
514 |
|
|
always @(posedge i_data_clk)
|
515 |
|
|
if ((i_ce)&&(!dr_stopped))
|
516 |
|
|
mem[waddr] <= wr_piped_data;
|
517 |
|
|
|
518 |
12 |
dgisselq |
//
|
519 |
|
|
// Clock transfer of the status signals
|
520 |
|
|
//
|
521 |
|
|
wire bw_stopped, bw_triggered, bw_primed;
|
522 |
|
|
generate
|
523 |
|
|
if (SYNCHRONOUS > 0)
|
524 |
|
|
begin
|
525 |
|
|
assign bw_stopped = dr_stopped;
|
526 |
|
|
assign bw_triggered = dr_triggered;
|
527 |
|
|
assign bw_primed = dr_primed;
|
528 |
|
|
end else begin
|
529 |
|
|
// These aren't a problem, since none of these are strobe
|
530 |
|
|
// signals. They goes from low to high, and then stays high
|
531 |
|
|
// for many clocks. Swapping is thus easy--two flip flops to
|
532 |
|
|
// protect against meta-stability and we're done.
|
533 |
|
|
//
|
534 |
|
|
(* ASYNC_REG = "TRUE" *) reg [2:0] q_oflags;
|
535 |
|
|
reg [2:0] r_oflags;
|
536 |
|
|
initial q_oflags = 3'h0;
|
537 |
|
|
initial r_oflags = 3'h0;
|
538 |
13 |
dgisselq |
always @(posedge bus_clock)
|
539 |
12 |
dgisselq |
if (bw_reset_request)
|
540 |
|
|
begin
|
541 |
|
|
q_oflags <= 3'h0;
|
542 |
|
|
r_oflags <= 3'h0;
|
543 |
|
|
end else begin
|
544 |
|
|
q_oflags <= { dr_stopped, dr_triggered, dr_primed };
|
545 |
|
|
r_oflags <= q_oflags;
|
546 |
|
|
end
|
547 |
|
|
|
548 |
|
|
assign bw_stopped = r_oflags[2];
|
549 |
|
|
assign bw_triggered = r_oflags[1];
|
550 |
|
|
assign bw_primed = r_oflags[0];
|
551 |
|
|
end endgenerate
|
552 |
|
|
|
553 |
|
|
// Reads use the bus clock
|
554 |
14 |
dgisselq |
initial raddr = 0;
|
555 |
13 |
dgisselq |
always @(posedge bus_clock)
|
556 |
12 |
dgisselq |
begin
|
557 |
13 |
dgisselq |
if ((bw_reset_request)||(write_to_control))
|
558 |
12 |
dgisselq |
raddr <= 0;
|
559 |
|
|
else if ((read_from_data)&&(bw_stopped))
|
560 |
13 |
dgisselq |
raddr <= raddr + 1'b1; // Data read, when stopped
|
561 |
12 |
dgisselq |
end
|
562 |
|
|
|
563 |
13 |
dgisselq |
reg [(LGMEM-1):0] this_addr;
|
564 |
|
|
always @(posedge bus_clock)
|
565 |
14 |
dgisselq |
if ((bw_stopped)&&(read_from_data))
|
566 |
|
|
this_addr <= raddr + waddr + 1'b1;
|
567 |
|
|
else
|
568 |
|
|
this_addr <= raddr + waddr;
|
569 |
12 |
dgisselq |
|
570 |
|
|
reg [31:0] nxt_mem;
|
571 |
13 |
dgisselq |
always @(posedge bus_clock)
|
572 |
14 |
dgisselq |
if (read_from_data)
|
573 |
13 |
dgisselq |
nxt_mem <= mem[this_addr];
|
574 |
12 |
dgisselq |
|
575 |
13 |
dgisselq |
wire [19:0] full_holdoff;
|
576 |
|
|
assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff;
|
577 |
|
|
generate if (HOLDOFFBITS < 20)
|
578 |
|
|
assign full_holdoff[19:(HOLDOFFBITS)] = 0;
|
579 |
|
|
endgenerate
|
580 |
12 |
dgisselq |
|
581 |
13 |
dgisselq |
reg [31:0] o_bus_data;
|
582 |
12 |
dgisselq |
wire [4:0] bw_lgmem;
|
583 |
|
|
assign bw_lgmem = LGMEM;
|
584 |
13 |
dgisselq |
always @(posedge bus_clock)
|
585 |
14 |
dgisselq |
if (rvalid[0])
|
586 |
|
|
begin
|
587 |
13 |
dgisselq |
if (!read_address) // Control register read
|
588 |
|
|
o_bus_data <= { bw_reset_request,
|
589 |
12 |
dgisselq |
bw_stopped,
|
590 |
|
|
bw_triggered,
|
591 |
|
|
bw_primed,
|
592 |
|
|
bw_manual_trigger,
|
593 |
|
|
bw_disable_trigger,
|
594 |
|
|
(raddr == {(LGMEM){1'b0}}),
|
595 |
|
|
bw_lgmem,
|
596 |
13 |
dgisselq |
full_holdoff };
|
597 |
|
|
else if (!bw_stopped) // read, prior to stopping
|
598 |
|
|
o_bus_data <= i_data;
|
599 |
12 |
dgisselq |
else // if (i_wb_addr) // Read from FIFO memory
|
600 |
13 |
dgisselq |
o_bus_data <= nxt_mem; // mem[raddr+waddr];
|
601 |
14 |
dgisselq |
end
|
602 |
12 |
dgisselq |
|
603 |
13 |
dgisselq |
assign S_AXI_RDATA = o_bus_data;
|
604 |
12 |
dgisselq |
|
605 |
|
|
reg br_level_interrupt;
|
606 |
|
|
initial br_level_interrupt = 1'b0;
|
607 |
13 |
dgisselq |
assign o_interrupt = (bw_stopped)&&(!bw_disable_trigger)
|
608 |
|
|
&&(!br_level_interrupt);
|
609 |
|
|
always @(posedge bus_clock)
|
610 |
14 |
dgisselq |
if ((bw_reset_complete)||(bw_reset_request))
|
611 |
|
|
br_level_interrupt<= 1'b0;
|
612 |
|
|
else
|
613 |
|
|
br_level_interrupt<= (bw_stopped)&&(!bw_disable_trigger);
|
614 |
12 |
dgisselq |
|
615 |
13 |
dgisselq |
// verilator lint_off UNUSED
|
616 |
|
|
// Make verilator happy
|
617 |
|
|
wire [44:0] unused;
|
618 |
|
|
assign unused = { S_AXI_WSTRB, S_AXI_ARPROT, S_AXI_AWPROT,
|
619 |
|
|
axi_awaddr[3:1], axi_araddr[3:1],
|
620 |
|
|
i_wb_data[30:28], i_wb_data[25:0] };
|
621 |
|
|
// verilator lint_on UNUSED
|
622 |
14 |
dgisselq |
`ifdef FORMAL
|
623 |
|
|
generate if (SYNCHRONOUS)
|
624 |
|
|
begin
|
625 |
|
|
|
626 |
|
|
always @(*)
|
627 |
|
|
assume(i_data_clk == S_AXI_ACLK);
|
628 |
|
|
|
629 |
|
|
end else begin
|
630 |
|
|
localparam CKSTEP_BITS = 3;
|
631 |
|
|
localparam [CKSTEP_BITS-1:0]
|
632 |
|
|
MAX_STEP = { 1'b0, {(CKSTEP_BITS-1){1'b1}} };
|
633 |
|
|
|
634 |
|
|
// "artificially" generate two clocks
|
635 |
|
|
`ifdef VERIFIC
|
636 |
|
|
(* gclk *) wire gbl_clock;
|
637 |
|
|
global clocking @(posedge gbl_clock); endclocking
|
638 |
|
|
`endif
|
639 |
|
|
|
640 |
|
|
(* anyconst *) wire [CKSTEP_BITS-1:0] f_data_step, f_bus_step;
|
641 |
|
|
reg [CKSTEP_BITS-1:0] f_data_count, f_bus_count;
|
642 |
|
|
|
643 |
|
|
always @(*)
|
644 |
|
|
begin
|
645 |
|
|
assume(f_data_step > 0);
|
646 |
|
|
assume(f_bus_step > 0);
|
647 |
|
|
assume(f_data_step <= MAX_STEP);
|
648 |
|
|
assume(f_bus_step <= MAX_STEP);
|
649 |
|
|
|
650 |
|
|
assume((f_data_step == MAX_STEP)
|
651 |
|
|
||(f_bus_step == MAX_STEP));
|
652 |
|
|
end
|
653 |
|
|
|
654 |
|
|
always @($global_clock)
|
655 |
|
|
begin
|
656 |
|
|
f_data_count <= f_data_count + f_data_step;
|
657 |
|
|
f_bus_count <= f_bus_count + f_bus_step;
|
658 |
|
|
|
659 |
|
|
assume(i_data_clk == f_data_count[CKSTEP_BITS-1]);
|
660 |
|
|
assume(bus_clock == f_bus_count[CKSTEP_BITS-1]);
|
661 |
|
|
end
|
662 |
|
|
|
663 |
|
|
always @($global_clock)
|
664 |
|
|
if (!$rose(i_data_clk))
|
665 |
|
|
begin
|
666 |
|
|
assume($stable(i_trigger));
|
667 |
|
|
assume($stable(i_data));
|
668 |
|
|
end
|
669 |
|
|
|
670 |
|
|
always @($global_clock)
|
671 |
|
|
if (!$rose(S_AXI_ACLK))
|
672 |
|
|
begin
|
673 |
|
|
assume($stable(S_AXI_ARESETN));
|
674 |
|
|
//
|
675 |
|
|
assume($stable(S_AXI_AWADDR));
|
676 |
|
|
assume($stable(S_AXI_AWPROT));
|
677 |
|
|
assume($stable(S_AXI_AWVALID));
|
678 |
|
|
//
|
679 |
|
|
assume($stable(S_AXI_WDATA));
|
680 |
|
|
assume($stable(S_AXI_WSTRB));
|
681 |
|
|
assume($stable(S_AXI_WVALID));
|
682 |
|
|
//
|
683 |
|
|
assume($stable(S_AXI_BREADY));
|
684 |
|
|
//
|
685 |
|
|
assume($stable(S_AXI_ARADDR));
|
686 |
|
|
assume($stable(S_AXI_ARPROT));
|
687 |
|
|
assume($stable(S_AXI_ARVALID));
|
688 |
|
|
//
|
689 |
|
|
assume($stable(S_AXI_RREADY));
|
690 |
|
|
//
|
691 |
|
|
end
|
692 |
|
|
|
693 |
|
|
end endgenerate
|
694 |
|
|
|
695 |
|
|
reg f_past_valid_bus, f_past_valid_gbl, f_past_valid_data;
|
696 |
|
|
initial { f_past_valid_bus, f_past_valid_gbl, f_past_valid_data }= 3'b0;
|
697 |
|
|
always @(posedge S_AXI_ACLK)
|
698 |
|
|
f_past_valid_bus = 1'b1;
|
699 |
|
|
|
700 |
|
|
generate if (!SYNCHRONOUS)
|
701 |
|
|
begin
|
702 |
|
|
always @($global_clock)
|
703 |
|
|
f_past_valid_gbl <= 1'b1;
|
704 |
|
|
|
705 |
|
|
always @(posedge i_data_clk)
|
706 |
|
|
f_past_valid_data = 1'b1;
|
707 |
|
|
|
708 |
|
|
always @(posedge i_data_clk)
|
709 |
|
|
if (f_past_valid_data)
|
710 |
|
|
assert($stable(o_interrupt));
|
711 |
|
|
|
712 |
|
|
always @($global_clock)
|
713 |
|
|
if ((f_past_valid_gbl)&&(!$rose(S_AXI_ACLK)))
|
714 |
|
|
begin
|
715 |
|
|
assert($stable(S_AXI_AWREADY));
|
716 |
|
|
assert($stable(S_AXI_ARREADY));
|
717 |
|
|
assert($stable(S_AXI_RDATA));
|
718 |
|
|
assert($stable(S_AXI_RRESP));
|
719 |
|
|
assert($stable(S_AXI_RVALID));
|
720 |
|
|
assert($stable(S_AXI_WREADY));
|
721 |
|
|
assert($stable(S_AXI_BRESP));
|
722 |
|
|
assert($stable(S_AXI_BVALID));
|
723 |
|
|
end
|
724 |
|
|
|
725 |
|
|
end else begin
|
726 |
|
|
|
727 |
|
|
always @(*)
|
728 |
|
|
f_past_valid_data = f_past_valid_bus;
|
729 |
|
|
always @(*)
|
730 |
|
|
f_past_valid_gbl = f_past_valid_bus;
|
731 |
|
|
|
732 |
|
|
end endgenerate
|
733 |
|
|
|
734 |
|
|
localparam F_LGDEPTH = 5;
|
735 |
|
|
wire [F_LGDEPTH-1:0] f_axi_rd_outstanding,
|
736 |
|
|
f_axi_wr_outstanding,
|
737 |
|
|
f_axi_awr_outstanding;
|
738 |
|
|
|
739 |
|
|
faxil_slave #(
|
740 |
|
|
// .C_S_AXI_DATA_WIDth(C_S_AXI_DATA_WIDTH),
|
741 |
|
|
// Width of S_AXI address bus
|
742 |
|
|
.C_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),
|
743 |
|
|
.F_LGDEPTH(F_LGDEPTH),
|
744 |
|
|
.F_OPT_HAS_CACHE(1'b0),
|
745 |
|
|
// .F_OPT_CLK2FFLOGIC(!SYNCHRONOUS),
|
746 |
|
|
.F_AXI_MAXWAIT(5'h6),
|
747 |
|
|
.F_AXI_MAXDELAY(5'h6),
|
748 |
|
|
) faxil_slave(
|
749 |
|
|
.i_clk(S_AXI_ACLK),
|
750 |
|
|
.i_axi_reset_n(S_AXI_ARESETN),
|
751 |
|
|
//
|
752 |
|
|
.i_axi_awaddr(S_AXI_AWADDR),
|
753 |
|
|
.i_axi_awprot(S_AXI_AWPROT),
|
754 |
|
|
.i_axi_awcache(4'h0),
|
755 |
|
|
.i_axi_awvalid(S_AXI_AWVALID),
|
756 |
|
|
.i_axi_awready(S_AXI_AWREADY),
|
757 |
|
|
//
|
758 |
|
|
.i_axi_wdata(S_AXI_WDATA),
|
759 |
|
|
.i_axi_wstrb(S_AXI_WSTRB),
|
760 |
|
|
.i_axi_wvalid(S_AXI_WVALID),
|
761 |
|
|
.i_axi_wready(S_AXI_WREADY),
|
762 |
|
|
//
|
763 |
|
|
.i_axi_bresp(S_AXI_BRESP),
|
764 |
|
|
.i_axi_bvalid(S_AXI_BVALID),
|
765 |
|
|
.i_axi_bready(S_AXI_BREADY),
|
766 |
|
|
//
|
767 |
|
|
.i_axi_araddr(S_AXI_ARADDR),
|
768 |
|
|
.i_axi_arprot(S_AXI_ARPROT),
|
769 |
|
|
.i_axi_arvalid(S_AXI_ARVALID),
|
770 |
|
|
.i_axi_arready(S_AXI_ARREADY),
|
771 |
|
|
.i_axi_arcache(4'h0),
|
772 |
|
|
//
|
773 |
|
|
.i_axi_rdata(S_AXI_RDATA),
|
774 |
|
|
.i_axi_rresp(S_AXI_RRESP),
|
775 |
|
|
.i_axi_rvalid(S_AXI_RVALID),
|
776 |
|
|
.i_axi_rready(S_AXI_RREADY),
|
777 |
|
|
//
|
778 |
|
|
.f_axi_rd_outstanding(f_axi_rd_outstanding),
|
779 |
|
|
.f_axi_wr_outstanding(f_axi_wr_outstanding),
|
780 |
|
|
.f_axi_awr_outstanding(f_axi_awr_outstanding));
|
781 |
|
|
|
782 |
|
|
always @(*)
|
783 |
|
|
begin
|
784 |
|
|
assert(f_axi_wr_outstanding == f_axi_awr_outstanding);
|
785 |
|
|
if (axi_bvalid)
|
786 |
|
|
assert(f_axi_wr_outstanding == 1);
|
787 |
|
|
else
|
788 |
|
|
assert(f_axi_wr_outstanding == 0);
|
789 |
|
|
if (|rvalid)
|
790 |
|
|
assert(f_axi_rd_outstanding == 1);
|
791 |
|
|
else
|
792 |
|
|
assert(f_axi_rd_outstanding == 0);
|
793 |
|
|
assert(rvalid != 2'b11);
|
794 |
|
|
end
|
795 |
|
|
|
796 |
|
|
always @(*)
|
797 |
|
|
if (dr_triggered)
|
798 |
|
|
assert(dr_primed);
|
799 |
|
|
|
800 |
|
|
always @(*)
|
801 |
|
|
if (dr_stopped)
|
802 |
|
|
assert((dr_primed)&&(dr_triggered));
|
803 |
|
|
|
804 |
|
|
reg dr_triggered, dr_primed;
|
805 |
|
|
wire dw_trigger;
|
806 |
|
|
assign dw_trigger = (dr_primed)&&(
|
807 |
|
|
((i_trigger)&&(!dw_disable_trigger))
|
808 |
|
|
||(dw_manual_trigger));
|
809 |
|
|
|
810 |
|
|
(* anyconst *) wire [(LGMEM-1):0] f_addr;
|
811 |
|
|
reg [31:0] f_data;
|
812 |
|
|
reg f_filled;
|
813 |
|
|
|
814 |
|
|
initial f_filled = 1'b0;
|
815 |
|
|
always @(posedge i_data_clk)
|
816 |
|
|
if (dw_reset)
|
817 |
|
|
f_filled <= 1'b0;
|
818 |
|
|
else if ((i_ce)&&(!dr_stopped)&&(waddr == f_addr))
|
819 |
|
|
f_filled <= 1'b1;
|
820 |
|
|
|
821 |
|
|
always @(posedge i_data_clk)
|
822 |
|
|
if (waddr > f_addr)
|
823 |
|
|
assert(f_filled);
|
824 |
|
|
|
825 |
|
|
always @(posedge i_data_clk)
|
826 |
|
|
if (!f_filled)
|
827 |
|
|
assert(!dr_primed);
|
828 |
|
|
|
829 |
|
|
always @(posedge i_data_clk)
|
830 |
|
|
if ((i_ce)&&(!dr_stopped)&&(waddr == f_addr))
|
831 |
|
|
f_data <= wr_piped_data;
|
832 |
|
|
|
833 |
|
|
always @(posedge i_data_clk)
|
834 |
|
|
if (f_filled)
|
835 |
|
|
assert(mem[f_addr] == f_data);
|
836 |
|
|
|
837 |
|
|
`endif
|
838 |
12 |
dgisselq |
endmodule
|