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dgisselq |
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##
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## Filename: Makefile
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##
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## Project: wbuart32, a full featured UART with simulator
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##
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## Purpose:
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##
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## Creator: Dan Gisselquist, Ph.D.
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## Gisselquist Technology, LLC
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##
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################################################################################
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##
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## Copyright (C) 2015-2016, Gisselquist Technology, LLC
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##
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## This program is free software (firmware): you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as published
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## by the Free Software Foundation, either version 3 of the License, or (at
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## your option) any later version.
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##
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## This program is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with this program. (It's in the $(ROOT)/doc directory, run make with no
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## target there if the PDF file isn't present.) If not, see
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## for a copy.
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##
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## License: GPL, v3, as defined and found on www.gnu.org,
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## http://www.gnu.org/licenses/gpl.html
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##
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##
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################################################################################
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##
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##
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CXX := g++
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FLAGS := -Wall -Og -g
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OBJDIR := obj-pc
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RTLD := ../verilog
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INCS := -I$(RTLD)/obj_dir/ -I/usr/share/verilator/include
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SOURCES := linetest.cpp
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VOBJDR := $(RTLD)/obj_dir
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VLIB := /usr/share/verilator/include/verilated.cpp
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SIMSRCS := linetest.cpp uartsim.cpp
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SIMOBJ := $(subst .cpp,.o,$(SIMSRCS))
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SIMOBJS:= $(addprefix $(OBJDIR)/,$(SIMOBJ))
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all: $(OBJDIR)/ linetest
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$(OBJDIR)/:
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@bash -c "if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi"
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$(OBJDIR)/uartsim.o: uartsim.cpp uartsim.h
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$(OBJDIR)/%.o: %.cpp
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$(CXX) $(FLAGS) $(INCS) -c $< -o $@
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linetest: $(OBJDIR)/linetest.o $(OBJDIR)/uartsim.o $(VOBJDR)/Vlinetest__ALL.a
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$(CXX) $(FLAGS) $(INCS) $^ $(VLIB) -o $@
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.PHONY: clean
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clean:
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rm ./linetest
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rm $(OBJDIR)/
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