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[/] [wbuart32/] [trunk/] [bench/] [formal/] [Makefile] - Blame information for rev 22

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1 20 dgisselq
################################################################################
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##
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## Filename:    Makefile
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##
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## Project:     wbuart32, a full featured UART with simulator
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##
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## Purpose:     To direct the formal verification of the UART (and FIFO)
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##              sources.
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##
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## Targets:     The default target, all, tests all of the components defined
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##              within this module.
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##
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## Creator:     Dan Gisselquist, Ph.D.
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##              Gisselquist Technology, LLC
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##
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################################################################################
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##
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## Copyright (C) 2017, Gisselquist Technology, LLC
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##
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## This program is free software (firmware): you can redistribute it and/or
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## modify it under the terms of  the GNU General Public License as published
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## by the Free Software Foundation, either version 3 of the License, or (at
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## your option) any later version.
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##
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## This program is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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## target there if the PDF file isn't present.)  If not, see
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##  for a copy.
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##
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## License:     GPL, v3, as defined and found on www.gnu.org,
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##              http://www.gnu.org/licenses/gpl.html
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##
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################################################################################
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##
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##
41 22 dgisselq
TESTS := ufifo txuartlite rxuartlite
42 20 dgisselq
.PHONY: $(TESTS)
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all: $(TESTS)
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RTL := ../../rtl
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SMTBMC  := yosys-smtbmc
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# SOLVER  := -s z3
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SOLVER  := -s yices
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# BMCARGS := --presat $(SOLVER)
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BMCARGS := $(SOLVER)
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INDARGS := $(SOLVER) -i
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FIFO  := ufifo
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TX    := txuartlite
54 22 dgisselq
RX    := rxuartlite
55 20 dgisselq
 
56 22 dgisselq
$(FIFO).smt2: $(RTL)/$(FIFO).v $(FIFO).ys
57 20 dgisselq
        yosys -ql $(FIFO).yslog -s $(FIFO).ys
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59 22 dgisselq
$(TX).smt2: $(RTL)/$(TX).v $(TX).ys
60 20 dgisselq
        yosys -ql $(TX).yslog -s $(TX).ys
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62 22 dgisselq
$(RX).smt2: $(RTL)/$(RX).v $(RX).ys
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        yosys -ql $(RX).yslog -s $(RX).ys
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65 20 dgisselq
$(FIFO) : $(FIFO).check
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$(FIFO).check: $(FIFO).smt2
67 22 dgisselq
        $(SMTBMC) --presat $(BMCARGS) -t 10 --dump-vcd $(FIFO).vcd $(FIFO).smt2
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        $(SMTBMC)          $(INDARGS) -t 10 --dump-vcd $(FIFO).vcd $(FIFO).smt2
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        touch $@
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$(TX) : $(TX).check
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$(TX).check: $(TX).smt2
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        $(SMTBMC) --presat $(BMCARGS) -t 90 --dump-vcd $(TX).vcd $(TX).smt2
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        $(SMTBMC)          $(INDARGS) -t 90 --dump-vcd $(TX).vcd $(TX).smt2
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        $(SMTBMC) -c $(SOLVER) -t 90 --dump-vcd $(TX).vcd $(TX).smt2
76 20 dgisselq
        touch $@
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78 22 dgisselq
$(RX) : $(RX).check
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$(RX).check: $(RX).sby $(RTL)/$(RX).v
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        sby -f $(RX).sby
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        touch $@
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83 22 dgisselq
 
84 20 dgisselq
.PHONY: clean
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clean:
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        rm -f  $(FIFO).smt2 $(FIFO)*.vcd
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        rm -f  $(TX).smt2   $(TX)*.vcd
88 22 dgisselq
        rm -rf $(RX)_one/   $(RX)_two/
89 20 dgisselq
        rm -f *.check

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