URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

[/] [wbuart32/] [trunk/] [bench/] [formal/] [rxuartlite.sby] - Blame information for rev 22

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[tasks]
one
two
 
[options]
mode prove
multiclock on
one: depth   20
two: depth  120
 
[engines]
smtbmc
 
[script]
one: read_verilog -D RXUARTLITE -formal rxuartlite.v
two: read_verilog -D RXUARTLITE -D PHASE_TWO -formal rxuartlite.v
chparam -set CLOCKS_PER_BAUD 16 rxuartlite
prep -top rxuartlite
# opt_merge -share_all
 
[files]
../../rtl/rxuartlite.v

Line No.	Rev	Author	Line
1	22	dgisselq	`[tasks]`
2			`one`
3			`two`
4
5			`[options]`
6			`mode prove`
7			`multiclock on`
8			`one: depth 20`
9			`two: depth 120`
10
11			`[engines]`
12			`smtbmc`
13
14			`[script]`
15			`one: read_verilog -D RXUARTLITE -formal rxuartlite.v`
16			`two: read_verilog -D RXUARTLITE -D PHASE_TWO -formal rxuartlite.v`
17			`chparam -set CLOCKS_PER_BAUD 16 rxuartlite`
18			`prep -top rxuartlite`
19			`# opt_merge -share_all`
20
21			`[files]`
22			`../../rtl/rxuartlite.v`

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Subversion Repositories wbuart32

[/] [wbuart32/] [trunk/] [bench/] [formal/] [rxuartlite.sby] - Blame information for rev 22