OpenCores
URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

[/] [wbuart32/] [trunk/] [bench/] [formal/] [rxuartlite.sby] - Blame information for rev 26

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 22 dgisselq
[tasks]
2 26 dgisselq
prf
3
cvr
4 22 dgisselq
 
5
[options]
6 26 dgisselq
prf: mode prove
7
cvr: mode cover
8 22 dgisselq
multiclock on
9 26 dgisselq
prf: depth  110
10
cvr: depth  720
11 22 dgisselq
 
12
[engines]
13 26 dgisselq
smtbmc boolector
14 22 dgisselq
 
15
[script]
16 26 dgisselq
prf: read -formal -DRXUARTLITE -D PHASE_TWO rxuartlite.v
17
cvr: read -formal -DRXUARTLITE -D PHASE_TWO rxuartlite.v
18 22 dgisselq
chparam -set CLOCKS_PER_BAUD 16 rxuartlite
19
prep -top rxuartlite
20
# opt_merge -share_all
21
 
22
[files]
23
../../rtl/rxuartlite.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.