URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

[/] [wbuart32/] [trunk/] [bench/] [formal/] [rxuartlite.ys] - Blame information for rev 22

Details | Compare with Previous | View Log


read_verilog -D TXUARTLITE -formal ../../rtl/rxuartlite.v
chparam -set CLOCKS_PER_BAUD 16
prep -top rxuartlite -nordff
clk2fflogic
opt -share_all
write_smt2 -wires rxuartlite.smt2

Line No.	Rev	Author	Line
1	22	dgisselq	`read_verilog -D TXUARTLITE -formal ../../rtl/rxuartlite.v`
2			`chparam -set CLOCKS_PER_BAUD 16`
3			`prep -top rxuartlite -nordff`
4			`clk2fflogic`
5			`opt -share_all`
6			`write_smt2 -wires rxuartlite.smt2`

Browse

Tools

Subversion Repositories wbuart32

[/] [wbuart32/] [trunk/] [bench/] [formal/] [rxuartlite.ys] - Blame information for rev 22