OpenCores
URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

[/] [wbuart32/] [trunk/] [bench/] [verilog/] [Makefile] - Blame information for rev 26

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
################################################################################
2
##
3
## Filename:    Makefile
4
##
5
## Project:     wbuart32, a full featured UART with simulator
6
##
7
## Purpose:     To direct the Verilator build of the Verilog portion of the
8
##              bench test.  The result is C++ code (built by Verilator), that
9
##      is then built (herein) into a library.
10
##
11 5 dgisselq
## ALTERNATE_PURPOSE:
12
##      All of the Verilog files within this directory may be made top level
13
##      files in their own right for the purpose of testing the UART capability
14
##      of your board.  Should you wish to test these as toplevel files, you
15
##      will need to remove the i_setup from the input, and set it to something
16
##      like:
17
##              wire    [29:0]  i_setup;
18 2 dgisselq
##
19 5 dgisselq
##              // If we have a 100MHz clock, then we can set up for a 115,200
20
##              // baud clock by setting i_setup to (100MHz / 115200) ~= 868.
21 18 dgisselq
##              // The upper bits of this number also set the protocol to
22 5 dgisselq
##              // one stop bit, no parity, and 8 data  bits.
23
##              assign  i_setup = 30'd868;      // 115,200 Baud 8N1
24
##
25
##      Using this purpose, the UART ports of a new piece of hardware may be
26
##      proven.  To do this,
27
##              1. get BLINKY working first--to prove that the clock works like
28
##                      you think it does.  Then, once BLINKY is running,
29
##              2. get helloworld working.  This requires only the clock and
30
##                      the output UART pin to work.
31
##              (Aside) 3. Once helloworld works, you should be able to get
32
##                      speechfifo to work with no further hassles.
33
##              4. After helloworld works, switch to getting linetest running on
34
##                      your hardware.  This will prove that you have not only
35
##                      the clock and output UART pin working, but that you also
36
##                      have the input UART pin working as well.
37
##
38
## Targets:     The default target of this makefile, all, builds the target
39
##              test, which includes the linetest Verilator library, the
40
##      helloworld Verilator library, and the speechfifo Verilator library--all
41
##      necessary for bench testing using the C++ files in bench/cpp.
42
##
43 2 dgisselq
## Creator:     Dan Gisselquist, Ph.D.
44
##              Gisselquist Technology, LLC
45
##
46
################################################################################
47
##
48
## Copyright (C) 2015-2016, Gisselquist Technology, LLC
49
##
50
## This program is free software (firmware): you can redistribute it and/or
51
## modify it under the terms of  the GNU General Public License as published
52
## by the Free Software Foundation, either version 3 of the License, or (at
53
## your option) any later version.
54
##
55
## This program is distributed in the hope that it will be useful, but WITHOUT
56
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
57
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
58
## for more details.
59
##
60
## You should have received a copy of the GNU General Public License along
61 18 dgisselq
## with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
62 2 dgisselq
## target there if the PDF file isn't present.)  If not, see
63
##  for a copy.
64
##
65
## License:     GPL, v3, as defined and found on www.gnu.org,
66
##              http://www.gnu.org/licenses/gpl.html
67
##
68
################################################################################
69
##
70
##
71 26 dgisselq
.PHONY: all
72
all:    test tags
73 2 dgisselq
YYMMDD=`date +%Y%m%d`
74
CXX   := g++
75
FBDIR := .
76
VDIRFB:= $(FBDIR)/obj_dir
77
RTLDR := ../../rtl
78 18 dgisselq
VERILATOR := verilator
79 26 dgisselq
VFLAGS := -Wall --MMD --trace -y $(RTLDR) -cc
80 2 dgisselq
 
81 5 dgisselq
.PHONY: test testline testhello speechfifo
82
test: testline testhello speechfifo
83 26 dgisselq
testline:   $(VDIRFB)/Vlinetest__ALL.a
84
testhello:  $(VDIRFB)/Vhelloworld__ALL.a
85 5 dgisselq
speechfifo: $(VDIRFB)/Vspeechfifo__ALL.a
86 2 dgisselq
 
87 26 dgisselq
$(VDIRFB)/Vlinetest__ALL.a:   $(VDIRFB)/Vlinetest.cpp
88
$(VDIRFB)/Vhelloworld__ALL.a: $(VDIRFB)/Vhelloworld.cpp
89
$(VDIRFB)/Vspeechfifo__ALL.a: $(VDIRFB)/Vspeechfifo.cpp
90 2 dgisselq
 
91 26 dgisselq
$(VDIRFB)/V%.mk:  $(VDIRFB)/%.h
92
$(VDIRFB)/V%.h:   $(VDIRFB)/%.cpp
93
$(VDIRFB)/V%.cpp: $(FBDIR)/%.v
94 18 dgisselq
        $(VERILATOR) $(VFLAGS) $*.v
95 2 dgisselq
 
96 26 dgisselq
$(VDIRFB)/V%__ALL.a: $(VDIRFB)/V%.cpp
97 2 dgisselq
        cd $(VDIRFB); make -f V$*.mk
98
 
99 26 dgisselq
tags: $(wildcard *.v) $(wildcard $(RTLDR)/*.v)
100
        ctags *.v $(RTLDR)/*.v
101
 
102 2 dgisselq
.PHONY: clean
103
clean:
104 26 dgisselq
        rm -rf tags $(VDIRFB)/
105 2 dgisselq
 
106 26 dgisselq
DEPS := $(wildcard $(VDIRFB)/*.d)
107
 
108
ifneq ($(MAKECMDGOALS),clean)
109
ifneq ($(DEPS),)
110
include $(DEPS)
111 18 dgisselq
endif
112 26 dgisselq
endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.