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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: linetest.v
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//
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// Project: wbuart32, a full featured UART with simulator
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//
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// Purpose: To test that the txuart and rxuart modules work properly, by
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// buffering one line's worth of input, and then piping that line
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// to the transmitter while (possibly) receiving a new line.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module linetest(i_clk, i_setup, i_uart, o_uart);
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input i_clk;
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input [29:0] i_setup;
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input i_uart;
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output wire o_uart;
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reg [7:0] buffer [0:255];
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reg [7:0] head, tail;
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reg pwr_reset;
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initial pwr_reset = 1'b1;
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always @(posedge i_clk)
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pwr_reset = 1'b0;
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wire rx_stb, rx_break, rx_perr, rx_ferr, rx_ignored;
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wire [7:0] rx_data;
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rxuart receiver(i_clk, pwr_reset, i_setup, i_uart, rx_stb, rx_data,
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rx_break, rx_perr, rx_ferr, rx_ignored);
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wire [7:0] nxt_head;
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assign nxt_head = head + 8'h01;
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always @(posedge i_clk)
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buffer[head] <= rx_data;
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initial head= 8'h00;
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always @(posedge i_clk)
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if (pwr_reset)
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head <= 8'h00;
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else if ((rx_stb)&&(!rx_break)&&(!rx_perr)&&(!rx_ferr)&&(nxt_head != tail))
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head <= nxt_head;
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wire [7:0] nused;
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reg [7:0] lineend;
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reg run_tx;
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assign nused = head-tail;
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initial run_tx = 0;
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initial lineend = 0;
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always @(posedge i_clk)
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if (pwr_reset)
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begin
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run_tx <= 1'b0;
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lineend <= 8'h00;
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end else if ((rx_data == 8'h0a)&&(rx_stb))
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begin
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lineend <= head+8'h1;
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run_tx <= 1'b1;
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end else if ((!run_tx)&&(nused>8'd80)&&(head != tail))
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begin
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lineend <= head;
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run_tx <= 1'b1;
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end else if (tail == lineend)
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run_tx <= 1'b0;
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wire tx_break, tx_busy;
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assign tx_break = 1'b0;
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reg [7:0] tx_data;
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reg tx_stb;
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always @(posedge i_clk)
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tx_data <= buffer[tail];
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initial tx_stb = 1'b0;
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always @(posedge i_clk)
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tx_stb <= run_tx;
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initial tail = 8'h00;
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always @(posedge i_clk)
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if(pwr_reset)
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tail <= 8'h00;
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else if ((tx_stb)&&(!tx_busy))
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tail <= tail + 8'h01;
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txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
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tx_stb, tx_data, o_uart, tx_busy);
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endmodule
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