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[/] [wbuart32/] [trunk/] [rtl/] [rxuart.v] - Blame information for rev 18

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////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    rxuart.v
4
//
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// Project:     wbuart32, a full featured UART with simulator
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//
7
// Purpose:     Receive and decode inputs from a single UART line.
8
//
9
//
10
//      To interface with this module, connect it to your system clock,
11
//      pass it the 32 bit setup register (defined below) and the UART
12
//      input.  When data becomes available, the o_wr line will be asserted
13
//      for one clock cycle.  On parity or frame errors, the o_parity_err
14
//      or o_frame_err lines will be asserted.  Likewise, on a break 
15
//      condition, o_break will be asserted.  These lines are self clearing.
16
//
17
//      There is a synchronous reset line, logic high.
18
//
19
//      Now for the setup register.  The register is 32 bits, so that this
20
//      UART may be set up over a 32-bit bus.
21
//
22 14 dgisselq
//      i_setup[30]     True if we are not using hardware flow control.  This bit
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//              is ignored within this module, as any receive hardware flow
24
//              control will need to be implemented elsewhere.
25
//
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//      i_setup[29:28]  Indicates the number of data bits per word.  This will
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//              either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
28
//              for a six bit word, or 2'b11 for a five bit word.
29 2 dgisselq
//
30
//      i_setup[27]     Indicates whether or not to use one or two stop bits.
31
//              Set this to one to expect two stop bits, zero for one.
32
//
33
//      i_setup[26]     Indicates whether or not a parity bit exists.  Set this
34
//              to 1'b1 to include parity.
35
//
36
//      i_setup[25]     Indicates whether or not the parity bit is fixed.  Set
37
//              to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
38
//              parity to be set based upon data.  (Both assume the parity
39
//              enable value is set.)
40
//
41
//      i_setup[24]     This bit is ignored if parity is not used.  Otherwise,
42
//              in the case of a fixed parity bit, this bit indicates whether
43
//              mark (1'b1) or space (1'b0) parity is used.  Likewise if the
44
//              parity is not fixed, a 1'b1 selects even parity, and 1'b0
45
//              selects odd.
46
//
47
//      i_setup[23:0]   Indicates the speed of the UART in terms of clocks.
48
//              So, for example, if you have a 200 MHz clock and wish to
49
//              run your UART at 9600 baud, you would take 200 MHz and divide
50
//              by 9600 to set this value to 24'd20834.  Likewise if you wished
51
//              to run this serial port at 115200 baud from a 200 MHz clock,
52
//              you would set the value to 24'd1736
53
//
54
//      Thus, to set the UART for the common setting of an 8-bit word, 
55
//      one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
56
//      would want to set the setup value to:
57
//
58
//      32'h0006c8              // For 115,200 baud, 8 bit, no parity
59
//      32'h005161              // For 9600 baud, 8 bit, no parity
60
//      
61
//
62
//
63
// Creator:     Dan Gisselquist, Ph.D.
64
//              Gisselquist Technology, LLC
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//
66
////////////////////////////////////////////////////////////////////////////////
67
//
68
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
69
//
70
// This program is free software (firmware): you can redistribute it and/or
71
// modify it under the terms of  the GNU General Public License as published
72
// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
74
//
75
// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
77
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
78
// for more details.
79
//
80
// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
85
// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
87
//
88
//
89
////////////////////////////////////////////////////////////////////////////////
90
//
91
//
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`default_nettype        none
93
//
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// States: (@ baud counter == 0)
95
//      0        First bit arrives
96
//      ..7     Bits arrive
97
//      8       Stop bit (x1)
98
//      9       Stop bit (x2)
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//      c       break condition
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//      d       Waiting for the channel to go high
101
//      e       Waiting for the reset to complete
102
//      f       Idle state
103
`define RXU_BIT_ZERO            4'h0
104
`define RXU_BIT_ONE             4'h1
105
`define RXU_BIT_TWO             4'h2
106
`define RXU_BIT_THREE           4'h3
107
`define RXU_BIT_FOUR            4'h4
108
`define RXU_BIT_FIVE            4'h5
109
`define RXU_BIT_SIX             4'h6
110
`define RXU_BIT_SEVEN           4'h7
111
`define RXU_PARITY              4'h8
112
`define RXU_STOP                4'h9
113
`define RXU_SECOND_STOP         4'ha
114
// Unused 4'hb
115
// Unused 4'hc
116
`define RXU_BREAK               4'hd
117
`define RXU_RESET_IDLE          4'he
118
`define RXU_IDLE                4'hf
119
 
120 5 dgisselq
module rxuart(i_clk, i_reset, i_setup, i_uart_rx, o_wr, o_data, o_break,
121 2 dgisselq
                        o_parity_err, o_frame_err, o_ck_uart);
122 9 dgisselq
        parameter [30:0] INITIAL_SETUP = 31'd868;
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        // 8 data bits, no parity, (at least 1) stop bit
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        input   wire            i_clk, i_reset;
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        /* verilator lint_off UNUSED */
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        input   wire    [30:0]   i_setup;
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        /* verilator lint_on UNUSED */
128 17 dgisselq
        input   wire            i_uart_rx;
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        output  reg             o_wr;
130
        output  reg     [7:0]    o_data;
131
        output  reg             o_break;
132
        output  reg             o_parity_err, o_frame_err;
133
        output  wire            o_ck_uart;
134
 
135
 
136
        wire    [27:0]   clocks_per_baud, break_condition, half_baud;
137
        wire    [1:0]    data_bits;
138
        wire            use_parity, parity_even, dblstop, fixd_parity;
139
        reg     [29:0]   r_setup;
140 7 dgisselq
        reg     [3:0]    state;
141 5 dgisselq
 
142 2 dgisselq
        assign  clocks_per_baud = { 4'h0, r_setup[23:0] };
143 9 dgisselq
        // assign hw_flow_control = !r_setup[30];
144 2 dgisselq
        assign  data_bits   = r_setup[29:28];
145
        assign  dblstop     = r_setup[27];
146
        assign  use_parity  = r_setup[26];
147
        assign  fixd_parity = r_setup[25];
148
        assign  parity_even = r_setup[24];
149
        assign  break_condition = { r_setup[23:0], 4'h0 };
150 5 dgisselq
        assign  half_baud = { 5'h00, r_setup[23:1] }-28'h1;
151
        reg     [27:0]   baud_counter;
152
        reg             zero_baud_counter;
153 2 dgisselq
 
154 5 dgisselq
 
155
        // Since this is an asynchronous receiver, we need to register our
156
        // input a couple of clocks over to avoid any problems with 
157
        // metastability.  We do that here, and then ignore all but the
158
        // ck_uart wire.
159 2 dgisselq
        reg     q_uart, qq_uart, ck_uart;
160
        initial q_uart  = 1'b0;
161
        initial qq_uart = 1'b0;
162
        initial ck_uart = 1'b0;
163
        always @(posedge i_clk)
164
        begin
165 5 dgisselq
                q_uart <= i_uart_rx;
166 2 dgisselq
                qq_uart <= q_uart;
167
                ck_uart <= qq_uart;
168
        end
169 5 dgisselq
 
170
        // In case anyone else wants this clocked, stabilized value, we
171
        // offer it on our output.
172 2 dgisselq
        assign  o_ck_uart = ck_uart;
173
 
174 5 dgisselq
        // Keep track of the number of clocks since the last change.
175
        //
176
        // This is used to determine if we are in either a break or an idle
177
        // condition, as discussed further below.
178 2 dgisselq
        reg     [27:0]   chg_counter;
179
        initial chg_counter = 28'h00;
180
        always @(posedge i_clk)
181
                if (i_reset)
182
                        chg_counter <= 28'h00;
183
                else if (qq_uart != ck_uart)
184
                        chg_counter <= 28'h00;
185
                else if (chg_counter < break_condition)
186
                        chg_counter <= chg_counter + 1;
187
 
188 5 dgisselq
        // Are we in a break condition?
189
        //
190
        // A break condition exists if the line is held low for longer than
191
        // a data word.  Hence, we keep track of when the last change occurred.
192
        // If it was more than break_condition clocks ago, and the current input
193
        // value is a 0, then we're in a break--and nothing can be read until
194
        // the line idles again.
195 2 dgisselq
        initial o_break    = 1'b0;
196
        always @(posedge i_clk)
197
                o_break <= ((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0;
198 5 dgisselq
 
199
        // Are we between characters?
200
        //
201
        // The opposite of a break condition is where the line is held high
202
        // for more clocks than would be in a character.  When this happens,
203
        // we know we have synchronization--otherwise, we might be sampling
204
        // from within a data word.
205
        //
206
        // This logic is used later to hold the RXUART in a reset condition
207
        // until we know we are between data words.  At that point, we should
208
        // be able to hold on to our synchronization.
209
        reg     line_synch;
210
        initial line_synch = 1'b0;
211 2 dgisselq
        always @(posedge i_clk)
212
                line_synch <= ((chg_counter >= break_condition)&&(ck_uart));
213
 
214 5 dgisselq
        // Are we in the middle of a baud iterval?  Specifically, are we
215
        // in the middle of a start bit?  Set this to high if so.  We'll use
216
        // this within our state machine to transition out of the IDLE
217
        // state.
218
        reg     half_baud_time;
219
        initial half_baud_time = 0;
220
        always @(posedge i_clk)
221
                half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud);
222
 
223
 
224
        // Allow our controlling processor to change our setup at any time
225
        // outside of receiving/processing a character.
226 9 dgisselq
        initial r_setup     = INITIAL_SETUP[29:0];
227 5 dgisselq
        always @(posedge i_clk)
228
                if (state >= `RXU_RESET_IDLE)
229 9 dgisselq
                        r_setup <= i_setup[29:0];
230 5 dgisselq
 
231
 
232
        // Our monster state machine.  YIKES!
233
        //
234
        // Yeah, this may be more complicated than it needs to be.  The basic
235
        // progression is:
236
        //      RESET -> RESET_IDLE -> (when line is idle) -> IDLE
237
        //      IDLE -> bit 0 -> bit 1 -> bit_{ndatabits} -> 
238
        //              (optional) PARITY -> STOP -> (optional) SECOND_STOP
239
        //              -> IDLE
240
        //      ANY -> (on break) BREAK -> IDLE
241
        //
242
        // There are 16 states, although all are not used.  These are listed
243
        // at the top of this file.
244
        //
245
        //      Logic inputs (12):      (I've tried to minimize this number)
246
        //              state   (4)
247
        //              i_reset
248
        //              line_synch
249
        //              o_break
250
        //              ckuart
251
        //              half_baud_time
252
        //              zero_baud_counter
253
        //              use_parity
254
        //              dblstop
255
        //      Logic outputs (4):
256
        //              state
257
        //
258 2 dgisselq
        initial state = `RXU_RESET_IDLE;
259
        always @(posedge i_clk)
260
        begin
261
                if (i_reset)
262
                        state <= `RXU_RESET_IDLE;
263 5 dgisselq
                else if (state == `RXU_RESET_IDLE)
264 2 dgisselq
                begin
265
                        if (line_synch)
266
                                // Goto idle state from a reset
267
                                state <= `RXU_IDLE;
268
                        else // Otherwise, stay in this condition 'til reset
269
                                state <= `RXU_RESET_IDLE;
270
                end else if (o_break)
271
                begin // We are in a break condition
272
                        state <= `RXU_BREAK;
273
                end else if (state == `RXU_BREAK)
274
                begin // Goto idle state following return ck_uart going high
275
                        if (ck_uart)
276
                                state <= `RXU_IDLE;
277
                        else
278
                                state <= `RXU_BREAK;
279
                end else if (state == `RXU_IDLE)
280
                begin // Idle state, independent of baud counter
281
                        if ((~ck_uart)&&(half_baud_time))
282
                        begin
283
                                // We are in the center of a valid start bit
284
                                case (data_bits)
285
                                2'b00: state <= `RXU_BIT_ZERO;
286
                                2'b01: state <= `RXU_BIT_ONE;
287
                                2'b10: state <= `RXU_BIT_TWO;
288
                                2'b11: state <= `RXU_BIT_THREE;
289
                                endcase
290
                        end else // Otherwise, just stay here in idle
291
                                state <= `RXU_IDLE;
292
                end else if (zero_baud_counter)
293
                begin
294
                        if (state < `RXU_BIT_SEVEN)
295
                                // Data arrives least significant bit first.
296
                                // By the time this is clocked in, it's what
297
                                // you'll have.
298
                                state <= state + 1;
299 5 dgisselq
                        else if (state == `RXU_BIT_SEVEN)
300 2 dgisselq
                                state <= (use_parity) ? `RXU_PARITY:`RXU_STOP;
301 5 dgisselq
                        else if (state == `RXU_PARITY)
302 2 dgisselq
                                state <= `RXU_STOP;
303 5 dgisselq
                        else if (state == `RXU_STOP)
304 2 dgisselq
                        begin // Stop (or parity) bit(s)
305 5 dgisselq
                                if (~ck_uart) // On frame error, wait 4 ch idle
306 2 dgisselq
                                        state <= `RXU_RESET_IDLE;
307
                                else if (dblstop)
308
                                        state <= `RXU_SECOND_STOP;
309
                                else
310
                                        state <= `RXU_IDLE;
311
                        end else // state must equal RX_SECOND_STOP
312
                        begin
313 5 dgisselq
                                if (~ck_uart) // On frame error, wait 4 ch idle
314 2 dgisselq
                                        state <= `RXU_RESET_IDLE;
315 5 dgisselq
                                else
316 2 dgisselq
                                        state <= `RXU_IDLE;
317
                        end
318
                end
319
        end
320
 
321 5 dgisselq
        // Data bit capture logic.
322
        //
323
        // This is drastically simplified from the state machine above, based
324
        // upon: 1) it doesn't matter what it is until the end of a captured
325
        // byte, and 2) the data register will flush itself of any invalid
326
        // data in all other cases.  Hence, let's keep it real simple.
327
        // The only trick, though, is that if we have parity, then the data
328
        // register needs to be held through that state without getting
329
        // updated.
330
        reg     [7:0]    data_reg;
331
        always @(posedge i_clk)
332
                if ((zero_baud_counter)&&(state != `RXU_PARITY))
333
                        data_reg <= { ck_uart, data_reg[7:1] };
334
 
335
        // Parity calculation logic
336
        //
337
        // As with the data capture logic, all that must be known about this
338
        // bit is that it is the exclusive-OR of all bits prior.  The first
339
        // of those will follow idle, so we set ourselves to zero on idle.
340
        // Then, as we walk through the states of a bit, all will adjust this
341
        // value up until the parity bit, where the value will be read.  Setting
342
        // it then or after will be irrelevant, so ... this should be good
343
        // and simplified.  Note--we don't need to adjust this on reset either,
344
        // since the reset state will lead to the idle state where we'll be
345
        // reset before any transmission takes place.
346
        reg             calc_parity;
347
        always @(posedge i_clk)
348
                if (state == `RXU_IDLE)
349
                        calc_parity <= 0;
350
                else if (zero_baud_counter)
351
                        calc_parity <= calc_parity ^ ck_uart;
352
 
353
        // Parity error logic
354
        //
355
        // Set during the parity bit interval, read during the last stop bit
356
        // interval, cleared on BREAK, RESET_IDLE, or IDLE states.
357
        initial o_parity_err = 1'b0;
358
        always @(posedge i_clk)
359
                if ((zero_baud_counter)&&(state == `RXU_PARITY))
360
                begin
361
                        if (fixd_parity)
362
                                // Fixed parity bit--independent of any dat
363
                                // value.
364
                                o_parity_err <= (ck_uart ^ parity_even);
365
                        else if (parity_even)
366
                                // Parity even: The XOR of all bits including
367
                                // the parity bit must be zero.
368
                                o_parity_err <= (calc_parity != ck_uart);
369
                        else
370
                                // Parity odd: the parity bit must equal the
371
                                // XOR of all the data bits.
372
                                o_parity_err <= (calc_parity == ck_uart);
373
                end else if (state >= `RXU_BREAK)
374
                        o_parity_err <= 1'b0;
375
 
376
        // Frame error determination
377
        //
378
        // For the purpose of this controller, a frame error is defined as a
379
        // stop bit (or second stop bit, if so enabled) not being high midway
380
        // through the stop baud interval.   The frame error value is
381
        // immediately read, so we can clear it under all other circumstances.
382
        // Specifically, we want it clear in RXU_BREAK, RXU_RESET_IDLE, and
383
        // most importantly in RXU_IDLE.
384
        initial o_frame_err  = 1'b0;
385
        always @(posedge i_clk)
386
                if ((zero_baud_counter)&&((state == `RXU_STOP)
387
                                                ||(state == `RXU_SECOND_STOP)))
388
                        o_frame_err <= (o_frame_err)||(~ck_uart);
389
                else if ((zero_baud_counter)||(state >= `RXU_BREAK))
390
                        o_frame_err <= 1'b0;
391
 
392
        // Our data bit logic doesn't need nearly the complexity of all that
393
        // work above.  Indeed, we only need to know if we are at the end of
394
        // a stop bit, in which case we copy the data_reg into our output
395
        // data register, o_data.
396
        //
397
        // We would also set o_wr to be true when this is the case, but ... we
398
        // won't know if there is a frame error on the second stop bit for 
399
        // another baud interval yet.  So, instead, we set up the logic so that
400
        // we know on the next zero baud counter that we can write out.  That's
401
        // the purpose of pre_wr.
402
        initial o_data = 8'h00;
403
        reg     pre_wr;
404
        initial pre_wr = 1'b0;
405
        always @(posedge i_clk)
406
                if (i_reset)
407
                begin
408
                        pre_wr <= 1'b0;
409
                        o_data <= 8'h00;
410
                end else if ((zero_baud_counter)&&(state == `RXU_STOP))
411
                begin
412
                        pre_wr <= 1'b1;
413
                        case (data_bits)
414
                        2'b00: o_data <= data_reg;
415
                        2'b01: o_data <= { 1'b0, data_reg[7:1] };
416
                        2'b10: o_data <= { 2'b0, data_reg[7:2] };
417
                        2'b11: o_data <= { 3'b0, data_reg[7:3] };
418
                        endcase
419
                end else if ((zero_baud_counter)||(state == `RXU_IDLE))
420
                        pre_wr <= 1'b0;
421
 
422
        // Create an output strobe, true for one clock only, once we know
423
        // all we need to know.  o_data will be set on the last baud interval,
424
        // o_parity_err on the last parity baud interval (if it existed,
425
        // cleared otherwise, so ... we should be good to go here.)
426
        initial o_wr   = 1'b0;
427
        always @(posedge i_clk)
428
                if ((zero_baud_counter)||(state == `RXU_IDLE))
429
                        o_wr <= (pre_wr)&&(!i_reset);
430
                else
431
                        o_wr <= 1'b0;
432
 
433
        // The baud counter
434
        //
435
        // This is used as a "clock divider" if you will, but the clock needs
436
        // to be reset before any byte can be decoded.  In all other respects,
437
        // we set ourselves up for clocks_per_baud counts between baud
438
        // intervals.
439
        always @(posedge i_clk)
440
                if (i_reset)
441
                        baud_counter <= clocks_per_baud-28'h01;
442
                else if (zero_baud_counter)
443
                        baud_counter <= clocks_per_baud-28'h01;
444
                else case(state)
445
                        `RXU_RESET_IDLE:baud_counter <= clocks_per_baud-28'h01;
446
                        `RXU_BREAK:     baud_counter <= clocks_per_baud-28'h01;
447
                        `RXU_IDLE:      baud_counter <= clocks_per_baud-28'h01;
448
                        default:        baud_counter <= baud_counter-28'h01;
449
                endcase
450
 
451
        // zero_baud_counter
452
        //
453
        // Rather than testing whether or not (baud_counter == 0) within our
454
        // (already too complicated) state transition tables, we use
455
        // zero_baud_counter to pre-charge that test on the clock
456
        // before--cleaning up some otherwise difficult timing dependencies.
457 2 dgisselq
        initial zero_baud_counter = 1'b0;
458
        always @(posedge i_clk)
459 5 dgisselq
                if (state == `RXU_IDLE)
460
                        zero_baud_counter <= 1'b0;
461
                else
462 2 dgisselq
                zero_baud_counter <= (baud_counter == 28'h01);
463
 
464
 
465
endmodule
466
 
467
 

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