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Wire-Frame 3D Graphics Accelerator IP Core
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Project Monophony
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================================================
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Author: Kenji Ishimaru
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System Setup:
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ZedBoard
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Configuration Modes: JTAG(JP7-JP11 are all GND).
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Connect Display device to D-sub25 pin VGA output.
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Directories:
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rtl:
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zedboard: Dedicated RTL for ZedBoard system implementation.
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axi_cmn: AXI bridges
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fm_hvc: VGA Controller
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synth/zedboard:
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Vivado project data.
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The data is tested on the following Vivado versions,
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v2015.4(64-bit) Windows
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v2016.1(64-bit) Windows
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v2015.2(64-bit) Windows
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v2015.3(64-bit) Windows
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How to Build FPGA Data
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1. Run Vivado Console
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(For example, run the Windows command prompt, then execute settings64.bat
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in the Vivado installation directory.)
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2. Chenge direcroty to implement/synth/zedboard
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3. Run run.bat
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zed_base_wrapper.bit will be generated.
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How to build Xilinx SDK Project
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The following steps import existing demo application projects to Xilinx SDK.
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1. run launch_sdk.tcl. This tcl script imports hardware Specification.
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for Vivado 2015.4
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$vivado -m64 -mode batch -source launch_sdk_2015.4.tcl
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for Vivado 2016.x
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$vivado -m64 -mode batch -source launch_sdk_2016.x.tcl
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2. On the Xilnx SDK Workspace Launcher, set Workspace to
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"(your wf3d directry)/implement/synth/zedboard/sdk"
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3. Generate BSP by default settings
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Xilnx SDK->File->New->Board Support Package,
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Project name: standalone_bsp_0
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Use default location: ON
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Target Hardware:
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Hardware Platform: zed_base_wrapper_hw_platform_0
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CPU: ps7_cortexa9_0
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Board Support Package OS:
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standalone
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Finally, standalone_bsp_0 will be generated.
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4. Import existing projects
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Xilnx SDK->File->Import...
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General->Existing Projects into Workspace
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Select root directory:"(your wf3d directry)/implement/synth/zedboard/sdk"
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After the projects are imported, the Project Explorer looks as follows:
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----------
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bear
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cubes
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hand
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space_ship
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simple_cube
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5. Build projects
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For all projects, set active configuration as Rlease:
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Build Configurations->Set Active->Release
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then, build all projects.
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Project->Build All
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**VERY IMPORTANT**
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Debug configuration is NOT implemented.
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Run the demos
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1. Run load_fpga.tcl. This tcl script downloads zed_base_wrapper.bit to ZedBoard
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$vivado -m64 -mode batch -source load_fpga.tcl
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2. On the Xilinx SDK, selsect one project and run the demo.
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for example, select simple_cube->right click->
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Run as->Launch on Hardware(System Debugger)
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